Bipolar Junction Transistor Amplifiers:Building Blocks for IC Amplifiers

Building Blocks for IC Amplifiers

This section discusses several single-stage amplifying circuits that may be combined with other stages to create a high-performance ampliﬁer.

Small-Signal Models

Most ampliﬁer circuits constrain the BJT stages to active region operation. In such cases, the models can be assumed to have constant elements that do not change with signal swing. These models are linear models. The quiescent or bias currents are ﬁrst found using a nonlinear model to allow the calculation of current-dependent element values for the small-signal model. For example, the dynamic resistance of the base-emitter diode, re, is given by

where IE is the DC emitter current. Once IE is found from a nonlinear DC equivalent circuit, the value of re is calculated and assumed to remain constant as the input signal is ampliﬁed.

The equivalent circuit [6] of Figure 23.5 shows the small-signal hybrid-p model that is closely related to the Gummel–Poon model and is used for AC analysis in the Spice program.

The capacitance, Cp, accounts for the diffusion capacitance and the emitter–base junction capacitance. The collector–base junction capacitance is designated Cµ. The resistance, rp, is equal to (b + 1)re. The transconductance, gm, is given by

RB, RE, and RC are the base, emitter, and collector resistances, respectively.

In many high-frequency, discrete ampliﬁer stages and in some high-frequency IC stages, a small value

of load resistance will be used. Approximate hand analysis can then be done by neglecting the ohmic resistances, RE and RC along with CCS, the collector to substrate capacitance. If the impedance ro is much larger than the load resistance, RL, of the high-frequency amplifying stage it can be considered an open circuit. The resulting model that allows relatively viable hand analysis is shown in Figure 23.6(a).

For small values of load resistances, the effect of the capacitance can be represented by an input Miller capacitance that appears in parallel with Cp. This simpliﬁed circuit now includes two separate loops as shown in Figure 23.6(b) and is referred to as the unilateral equivalent circuit. Typically, the input loop limits the bandwidth of the ampliﬁer stage. When driven with a signal generator having a source resistance of Rs, the upper 3-dB frequency can be approximated as

where A is the gain of the stage from point B¢ to the collector of the stage. Although Cµ is small, the resulting Miller effect increases this value to the point that it can dominate the expression for upper 3-dB frequency. In any case, it often has a major effect on frequency performance.

When higher impedance loads are used in a BJT as is often the case for IC ampliﬁer design, the Miller effect approach becomes less accurate and the performance must be simulated to achieve more accurate results. However, the unilateral circuit that includes Cµ and CCS from the collector to ground after reﬂecting the effects of Cm to the input loop can be used to approximate the ampliﬁer stage performance. Manually calculated results are generally within 5–10% of simulation results.

Active Loads

To achieve high voltage gains and eliminate load resistors, active loads are used in BJT IC ampliﬁer stages [4]. In a conventional common-emitter stage, the gain is limited by the size of the collector resistance. The midband voltage gain from base to collector of a common-emitter stage is given by

It would be possible to increase this voltage gain by increasing RC, however, making RC large can lead to some serious problems. A large collector load requires a low quiescent collector current to result in proper bias. This may lead to lower values of b, since current gain in a silicon transistor typically falls at low levels of emitter current. To achieve a voltage gain of 1000 V/V, a collector load of perhaps 100–200 kW might be required. The low collector current needed for proper bias, a few microamps, would lead to a low value of b and a very high value of re. The desired high voltage gain may not be achievable under these conditions.

It would be desirable if the collector load presented a low resistance to DC signals, but presented a high incremental resistance. This combination of impedances would result in a stable operating point along with a high gain. A perfect current source with inﬁnite incremental resistance along with a ﬁnite DC current ﬂow satisﬁes the requirements, but is not a practical solution. In contrast, circuits that approximate current sources are relatively easy to construct. A good approximation to the current source is obtained by using another transistor for the collector load of an amplifying transistor. Not only can this device present a low DC and high incremental impedance, it is a simple element to implement on a chip. This transistor that replaces the resistive load is referred to as an active load.

The circuit of Figure 23.7 demonstrates one type of BJT active load. The transistor Q1 is the amplifying element with Q2 acting as the load. Transistor Q1 looks into the collector of Q2. The incremental output impedance at the collector of a transistor having an emitter resistance in the low kW range can easily exceed 500 kW. With such a high impedance, Q2 approximates a current source.

The DC collector currents of both transistors are equal in magnitude. This magnitude can be set to a value that leads to a reasonable value of b. Since Q2 has a very high output impedance, the midband voltage gain will be determined primarily by the collector-to-emitter resistance of Q1 and can be calculated from

For an Early voltage of VA = 80 and VT = 0.026 V, a small-signal voltage gain exceeding -3000 V/V could result. In a normal application, this stage would drive a second stage. The input impedance of the second stage will load the output impedance of the ﬁrst stage, further lowering the gain. Depending on the input impedance of the second stage and the impedance of the active load stage, the gain magnitude may still exceed 1000 V/V.

The concept of an active load that presents a large incremental resistance while allowing a large DC quiescent current is important in IC design. In addition to the current source load just considered, the current mirror stage can also be used to provide the active load of a differential stage as discussed in the next subsection.

The Common Emitter Stage

A simple conﬁguration for an IC amplifying stage is shown in Figure 23.8. In this stage, the output impedance of the current mirror is not large enough to be considered an open circuit as it was in the circuit of Figure 23.7. Thus, the analysis will have to account for this element.

The high-frequency response of discrete BJT stages is often determined by the input circuit, including the Miller effect capacitance. The collector load resistance in a discrete stage is usually small enough that the output circuit does not affect the upper corner frequency. In the circuit of Figure 23.8, as in many IC ampliﬁer stages, the output impedance is very high compared with the discrete stage. For this circuit, the output impedance of the ampliﬁer consists of the output impedance of Q2 in parallel with that of Q1. This value will generally be several tens of kW.

The equivalent circuit of the ampliﬁer of Figure 23.8 is indicated in Figure 23.9. The value of Rout is

The upper corner frequency is now more difﬁcult to evaluate than that of the discrete circuit with its low value of collector load resistance. In the discrete circuit, the input loop generally determines the overall upper corner frequency of the circuit. Although the Miller effect will be much larger in the IC stage, lowering the upper corner frequency of the input loop, the corner frequency of the output loop will also be smaller due to the large value of Rout. Both frequencies may inﬂuence the overall upper corner frequency of the ampliﬁer.

As mentioned previously, it is difﬁcult to manually calculate the upper corner frequency of the stage and an accurate value is generally found by simulation. An approximation of the upper corner frequency can be manually found by reﬂecting the bridging capacitance, Cµ, to both the input and the output. The value reﬂected to the input side, across terminals b' and e, is

The approximate overall upper corner frequency, f2o, must be found by considering a two-pole response. The overall response is expressed as

Although this method is not as accurate as the simulation, results will often be within 5–10%.

The Common-Base Stage

The common-base stage shown in Figure 23.10 has an advantage and a disadvantage when compared with the common-emitter stage. The advantage is that the Miller effect, that is, the multiplication of apparent capacitance at the input, is essentially eliminated. The noninverting nature of the gain does not lead to an increased input capacitance. Furthermore, the capacitance between input (emitter) and output (collector) is generally negligible. The upper corner frequency is then higher than that of a comparable common-emitter stage.

The disadvantage is the low current and power gain of the common-base stage compared with the common-emitter stage. The low-frequency current gain for the common-base stage equal a and is slightly less than unity. In the common-emitter stage, the current gain equals b and may be over 200. Since voltage gain is similar for the two stages, the power gain is also much lower for the common-base stage. The input resistance at low frequencies is also much lower than that of the common-emitter stage and can load the previous stage.

Generally, the corner frequency of the input circuit is considerably higher than the corner frequency of the output circuit for high-gain IC stages and the overall upper corner frequency is approximated by fout-high. The midband voltage gain of the common-base and common-emitter stages decreases with increasing generator resistance. In multistage ampliﬁers, the generator resistance of one stage is the output resistance of the previous stage. If this value is large, the gain of the following stage may be small. Furthermore, the upper corner frequency of the common-emitter stage is affected by the generator resistance. Large

values of Rg can lead to small values of upper corner frequency.

The Emitter Follower

A stage that can be used to minimize the adverse effect on frequency response caused by a generator resistance is the emitter follower. Although this stage has a voltage gain near unity, it can be driven by a higher voltage gain stage while the emitter follower can drive a low impedance load. A typical stage is shown in Figure 23.11.

The output stage of the npn current mirror, Q2, serves as a high impedance load for the emitter follower, Q1. An equivalent circuit that represents the emitter follower of Figure 23.11 is indicated in Figure 23.12. For this circuit, g m1 = a1 /re » 1/re .

This circuit can be analyzed to result in a voltage gain of

The bandwidth is more difﬁcult to calculate since the response has one zero and two poles. The zero for the circuit of Figure 23.12 is typically larger than the lowest frequency pole. If these frequencies were canceled, the larger pole would determine the corner frequency. Since they do not cancel, the overall upper corner frequency is expected to be smaller than the larger pole frequency. An accurate calculation can be made from Eq. (23.25) when the parameters are known.

In high-frequency design, it must be recognized that the output impedance of the emitter follower can become inductive [7].

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