Bipolar Junction Transistor Circuits:Basic Operation of the BJT

By -
Basic Operation of the BJT

The BJT has three possible regions of operation: the active region, the cutoff region, and the saturation region. Amplifier circuits, creating output signals that are larger versions of the input signals, use the active region exclusively. Digital or switching circuits may pass through the active region while making transitions between the saturation and cutoff regions.

To understand the operation of the BJT as an amplifier or a switching circuit, we will discuss the simplified version of the device shown in Figure 10.2. The device shown is an npn device which consists of a p-doped material interfacing on opposite sides to an n-doped material. A pnp device can be created using an n-doped central region with p-doped interfacing regions. Since the npn type of BJT is more popular in present construction processes, the following discussion will center on this device.

The geometry of the device implied in Figure 10.2 is physically more like the earlier alloy transistor. This geometry is also capable of modeling the modern BJT (Figure 10.1) as the theory applies almost equally well to both geometries. Normally, some sort of load would appear in either the collector or emitter circuit, however this is not important to the initial discussion of BJT operation.

Bipolar Junction Transistor Circuits-0001

The Active Region

The circuit of Figure 10.2 is in the active region, that is, the emitter–base junction is forward-biased while the collector–base junction is reverse-biased. The current flow is controlled by the profile of electrons in the p-type base region. It is proportional to the slope or gradient of the free electron density in the base region. The well-known diffusion equation can be expressed as [3]

Bipolar Junction Transistor Circuits-0003

where q is the electronic charge, Dn the diffusion constant for electrons, A the cross-sectional area of the base region, W the width or thickness of the base region, and n(0) the density of electrons at the left edge of the base region. The negative sign reflects the fact that conventional current flow is opposite to the flow of the electrons.

The concentration of electrons at the left edge of the base region is given by

Bipolar Junction Transistor Circuits-0004

where q is the charge on an electron, k the Boltzmann’s constant, T the absolute temperature, and nbo the equilibrium concentration of electrons in the base region. While nbo is a small number, n(0) can be large for values of applied base to emitter voltages of 0.6 to 0.7 V. At room temperature, this equation can be written as

Bipolar Junction Transistor Circuits-0005

In Figure 10.2, the voltage VEB = -VBE.

A component of hole current also flows across the base–emitter junction from base to emitter. This component is rendered negligible compared to the electron component by doping the emitter region much more heavily than the base region.

As the concentration of electrons at the left edge of the base region increases, the gradient increases and the current flow across the base region increases. The density of electrons at x = 0 can be controlled by the voltage applied from emitter to base. Thus, this voltage controls the current flowing through the base region. In fact, since the density of electrons varies exponentially with the applied voltage from emitter to base (Eq. [10 .2]), the resulting current variation with voltage is also exponential.

The reservoir of electrons in the emitter region is unaffected by the applied emitter-to-base voltage as this voltage drops across the emitter–base depletion region. This applied voltage lowers the junction voltage as it opposes the built-in barrier voltage of the junction. This leads to the increase in electrons flowing from emitter to base.

The electrons injected into the base region represent electrons that were originally in the emitter. As these electrons leave the emitter, they are replaced by electrons from the voltage source, VEB. This current is called emitter current and its value is determined by the voltage applied to the junction. Of course, conventional current flows in the direction opposite to the electron flow.

The emitter electrons flow through the emitter, across the emitter–base depletion region, and into the base region. These electrons continue across the base region, across the collector–base depletion region, and through the collector. If no electrons were “lost” in the base region and if the hole flow from base to emitter were negligible, the current flow through the emitter would equal that through the collector. Unfortunately, there is some recombination of carriers in the base region. When electrons are injected into the base region from the emitter, space-charge neutrality is disturbed, pulling holes into the base region from the base terminal. These holes restore space-charge neutrality if they take on the same density throughout the base as the electrons. Some of these holes recombine with the free electrons in the base and the net flow of recombined holes into the base region leads to a small, but finite, value of base current. The electrons that recombine in the base region reduce the total electron flow to the collector. Because the base region is very narrow, only a small percentage of electrons traversing the base region recombine and the emitter current is reduced by a small percentage as it becomes collector current.

In a typical low-power BJT, the collector current might be 0.995 IE. The current gain from emitter to collector, IC/IE, is called a and is a function of the construction process for the BJT. Using Kirchhoff ’s current law, the base current is found to equal the emitter current minus the collector current. This gives

If a = 0.995, then IB = 0.005IE. Base current is very small compared with emitter or collector current. A parameter b is defined as the ratio of collector current to base current resulting in

Bipolar Junction Transistor Circuits-0006

This parameter represents the current gain from base to collector and can be quite high. For the value of a cited earlier, the value of b is 199.

The Cutoff Region

The cutoff region occurs when both junctions of the BJT are reverse-biased. In this situation, no electrons are injected across the emitter–base junction and no current flows through the base region. All terminals have zero current flow, prompting the name of this region. The BJT now approximates an open circuit from collector to emitter with high voltage drop, but no collector current flow.

The Saturation Region

If the voltage across the base–collector junction becomes forward-biased rather than reverse-biased, and the base–emitter junction is also forward-biased, the device is in the saturation region. This is usually accomplished by lowering the collector voltage to a value less than the base voltage. In this arrangement, the voltage drop from collector to emitter consists of the difference between the drop across the base–emitter junction and the drop across the base–collector junction. This voltage may be only 0.2 V. The BJT now approximates a short circuit from collector to emitter with little voltage drop, but possible high collector current.

Comments

Post a Comment

Popular posts from this blog

SRAM:Decoder and Word-Line Decoding Circuit [10–13].

By -
Image
Decoder and Word-Line Decoding Circuit [10–13] Two kinds of decoders are used in SRAM: the row decoder and the column decoder. Row decoders are needed to select one row of word-lines out of a set of rows in the array. A fast decoder can be implemented by using AND/NAND and OR/NOR gates. Figure 52.7 shows the schematic diagrams of static and dynamic AND gate decoders. The static NAND-type structure is chosen due to its low power consumption, that is, only the decoded row transitions. The dynamic structure is chosen due to its speed and power improvement over conventional static NAND gates. From a low-voltage operation standpoint, a dynamic NOR-base decoding would provide lower delay times through the decoder due to the limited amount of stacking of devices. Figure 52.8 shows circuit diagrams of dynamic NOR gates. The dynamic CMOS gate as shown in Figure 52.8(a) consists of input- NMOSs whose drain nodes are precharged to a high level by a PMOS when a clock signal Φ is at a low lev...
Read more

ASIC and Custom IC Cell Information Representation:GDS2

By -
Image
GDS2 The Graphical Design System (GDS) format is a binary format developed by Calma Company in 1971 to convey IC layout information between IC designers and fabricators. Calma presented GDS2 format, the improved version of GDS, in 1978. Finally in 1991, when Cadence acquired Calma, GDS2 rights were transferred to it. In the design process, after the completion of routing and placement, design rule check (DRC) and layout versus schematic (LVS) are performed to verify the final layout. Then the verified layout, dumped in a GDS2 file, is transferred to IC foundries for fabrication. GDS2 File Format GDS2 is a standard mask layout intermediate format containing a single cell or a library of cells each of which includes a number of geometrical objects such as boundaries, paths, boxes, etc. These objects correspond to different layers of a cell where each layer is specified by a layer number and data type [3]. The file format of GDS2 is in binary. A GDS2 file contains a number of variable...
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f...
Read more