Bipolar Junction Transistor Amplifiers:Operational Amplifiers

Operational Amplifiers

Very few circuits have had an impact on the electronics ﬁeld as great as that of the op amp circuit. This name is a shortened version of operational ampliﬁer, a term that has a rather speciﬁc meaning. As mentioned in an earlier section, before IC chips became available, operational ampliﬁers were expensive, high-performance ampliﬁers used primarily in a system called an analog computer. The analog computer was a real-time simulator that could simulate physical systems governed by differential equations. Exam- ples of such systems are circuits, mechanical systems, and chemical systems. One popular use of the analog computer was the simulation of automatic control systems. The control of a space vehicle had to be designed on paper before test ﬂights took place. The test ﬂights could then be used to ﬁne-tune the design. The analog computer was far more efﬁcient than the digital computer of the day in simulating differential equations and was far less costly.

The op amp was an important component of the analog computer that allowed several mathematical operations to be performed with electronic circuits. The op amp could be used to create a summing circuit, a difference circuit, a weighting circuit, or an integrating circuit. Using these capabilities, complex differential systems can be created with an output voltage that represents the physical output variable of the simulated system. The time variable may be scaled, but for many simulations, the output represents a real-time solution.

One of the key features of an op amp is the differential input to the ampliﬁer. This allows differences to be formed, and also allows the creation of a virtual ground or virtual short across the input terminals. This virtual short is used in summing several current signals into a node without affecting the other input current signals. These signals are then summed and easily converted into an output voltage.

The virtual ground also allows the formation of rather accurate integrals of the op amp using an additional resistor and capacitor. This feature is essential in the simulation of differential equations.

Other ampliﬁers are sometimes mistakenly referred to as op amps, but unless these ampliﬁers possess the capability to create a virtual ground and do mathematical operations, this is a misnomer.

The ﬁrst IC op amp was introduced by Fairchild Semiconductor Corporation in 1964. This chip, designated as µA702 or 702, was followed shortly by 709 which was the ﬁrst analog IC product to receive wide industry acceptance. The National LM101 and Fairchild 741 advanced the ﬁeld and eliminated the external compensation capacitors required for the earlier models. The ensuing popularity and low price of the 741 allowed op amps to be treated as a component rather than a subcircuit that must be designed.

Today, op amps are available in bipolar (BJT), complementary metal oxide semiconductor (CMOS), and BiCMOS (BJT/CMOS) technologies and designers have the option of including dozens of op amps and other circuits on a single chip. Modern op amps generally use the same architecture developed in the LM101/741 circuits with performance improvements resulting from improved processing techniques. The conﬁguration of an op amp offers one important advantage for IC ampliﬁers. This advantage is the op amp's ability to allow the input signal to be referenced to any DC voltage, including ground, within the allowed input range. This eliminates the need for a large coupling capacitor to isolate a DC input transducer from an ampliﬁer input.

A Classical IC Op Amp Architecture

While the technology used to implement op amps has changed considerably over the years, the basic architecture has remained remarkably constant [4]. This section will ﬁrst discuss that architecture and some approaches to its implementation. After this topic is considered, the subject will turn to methods of specifying ampliﬁer performance.

The architecture of many op amps appears as shown in Figure 23.19. The ﬁrst section is a differential ampliﬁer required by all op amps to allow a virtual ground and the implementation of mathematical operations. This stage is generally designed to have a very high differential voltage gain, perhaps a few thousand. The bandwidth is generally rather low as a result of the high voltage gain. In some cases, this

differential ampliﬁer will use an active load that will also convert the double-ended output of the differential stage into a single-ended output that will drive the second voltage ampliﬁer.

The second stage of Figure 23.19 is a single-ended voltage ampliﬁer with a relatively high voltage gain. This gain may reach values of 500 V/V. Often this stage is used to compensate the op amp, a topic that will be discussed later in this chapter. For now it is sufﬁcient to say that this stage will probably be an inverting stage that can multiply the apparent value of some capacitance placed between the input and output of the stage. The large capacitive load presented to the output of the ﬁrst stage due to the Miller effect will lead to a very low upper corner frequency, perhaps 10–100 Hz, for the ﬁrst stage.

The last stage is the output stage. It may be nothing more than an emitter follower that has a large current ampliﬁcation along with a voltage gain that is near unity. This stage will have a very high upper corner frequency.

A High-Gain Differential Stage

The normal way to achieve high voltage gains is to use an active load for the amplifying stages. The incremental resistance presented to the amplifying stage is very high, while the DC voltage across the active load is small. One popular choice for an active differential stage load is the current mirror. This load provides very high voltage gain and also converts the double-ended output signal into a single- ended signal referenced to ground. Figure 23.20 shows a block diagram of such an arrangement.

With no input signal applied to the differential stage, the tail current splits equally between Idiff1 and Idiff2. The input current to the mirror equals this value of Itail/2. This value is also mirrored to the output of the mirror giving Iout = Itail/2. We will assume that the voltage between the current mirror output and the second differential stage is approximately zero, although this assumption is unnecessary to achieve the correct result. When a signal is applied to the differential input, it may increase the current Idiff1 by a peak value of

When an incremental input signal is applied to the differential pair, half of this voltage will drop across each base–emitter junction of the pair. This results in equal incremental differential stage currents in the

If the output resistances of the mirror and differential stage are signiﬁcant, the voltage gain can be found by combining these resistances in parallel with the load resistance to form Reff = Rout ïïR. This resistance then replaces R in Eq. (23.49). The load resistance may, in fact, be the incremental input resistance of the following stage. Very large values of voltage gain can result from this conﬁguration. For the BJT, the transconductance is given by gm = a/re » 1/re.

While this expression for voltage gain is the same as that for the differential gain of a resistive load stage, given by Eq. (23.44), two signiﬁcant points should be made. First of all, the impedance R can be much greater than any resistive load that can be used in a differential stage. Large values of R in the differential stage would cause saturation of the stages for reasonable values of tail currents. In addition, large values of R are more difﬁcult to fabricate on an IC chip. The current mirror solves this problem. The second point is that the output voltage of the differential pair with a current mirror load is a single- ended output which can be applied to a following simple ampliﬁer stage. However, the rejection of common-mode variables caused by temperature change or power supply voltage changes is still in effect with the current mirror stage. If a resistive load differential stage must provide a single-ended output,

the gain drops by a factor of 2, compared with the double-ended output, and common-mode rejection no longer takes place.

The Second Amplifier Stage

Before the purpose of the second ampliﬁer stage can be fully understood, a discussion on circuit stability must take place.

Feedback and Stability of the Op Amp

The op amp is used in a feedback conﬁguration for essentially all amplifying applications. Because of nonideal or parasitic effects, it is possible for the feedback ampliﬁer to exhibit unstable behavior. Oscil- lations at the output of the ampliﬁer can exist, having no relationship to the applied input signal. This, of course, negates the desired linear operation of the ampliﬁer. It is necessary to eliminate any undesired oscillation signal from the ampliﬁer.

The open-loop voltage gain of a three-stage ampliﬁer such as that of Figure 23.19 may be represented by a gain function of

To check the stability of this circuit, a zero volt input signal (short circuit) can be applied to the noninverting input terminal. The loop gain from inverting terminal to output and back to inverting terminal can then be found with the noninverting terminal shorted to ground. When this is done, it is found [4] that the ampliﬁer is unstable for most practical values of values of RF and R2. The worst case condition occurs as R2 approaches inﬁnity and RF approaches zero as in the case of a unity-gain voltage buffer.

One measurement of stability is referred to as the phase margin. This quantity is deﬁned in terms of the phase shift of AF that exists when the magnitude of AF has dropped to unity. The number of degrees

less than -180° at this frequency is called the phase margin. Most ampliﬁers target a phase margin of 45° or more.

One possibility to achieve a reasonable phase margin is to intentionally modify one of the three upper corner frequencies of the op amp. For example, if the pole associated with the ﬁrst stage is lowered by several factors, the ampliﬁer can become stable, even when used as a unity-gain voltage buffer.

The frequency response of this gain is sketched in Figure 23.22 for a midband gain of 300,000. We note that the magnitude of this gain has fallen below a value of unity (0 dB) before the second upper corner frequency of 2 ´ 106 is reached. The phase shift of AF at the frequency where the magnitude has dropped to unity may be -130° resulting in a phase margin of 50°. Normally, engineers do not destroy bandwidth of a stage intentionally, however in this case it is necessary to stabilize the operation of the op amp in the feedback conﬁguration.

Lowering the upper corner frequency of one stage is not a trivial matter. While it may not need to be reduced to 10 rad/s in a practical op amp, it is often lowered to 10–100 Hz. A capacitor must be added to the appropriate point in the stage to drop this frequency, but a relatively large capacitor is required. In the early days of the IC op amp, the two terminals between which a capacitor was to be added were connected to two external pins of the chip. A discrete capacitor of sufﬁcient value was then added externally.

In 1967, the capacitor was added to the IC chip using the Miller effect to multiply the capacitor value. Returning to Figure 23.19, it is seen that a capacitor can be added between input and output of the second stage. This is typically a capacitor of value 30 pF that, due to the Miller effect, is multiplied by a factor of (A2 + 1) where -A2 is the gain of the second stage. The Miller capacitance is reﬂected to the input of the second stage that loads the output of the ﬁrst stage. This large effective capacitance, driven by the large output impedance of the ﬁrst stage produces a very low upper corner frequency for the ﬁrst stage.

In a 741 op amp design, the gain A2 is approximately -400 V/V. With a 30 pF capacitance bridging input to output, the effective capacitance at the input is ~0.012 mF. This creates a bandwidth for the op amp of 10 Hz or 62.8 rad/s.

This method of solving the instability problem is referred to as dominant pole compensation. The lower value of pole frequency is seen from Figure 23.22 to dominate the ampliﬁer performance up to frequencies above the useful range of gain.

It should be mentioned that op amps for speciﬁc applications may not need to be stabilized for the unity gain conﬁguration. The minimum gain required by the ampliﬁer may be 2 or 3 V/V or some other value that is easier to compensate. In such cases, the dominant pole need not be decreased to the level of the general purpose op amp. The resulting frequency performance of the op amp can then be higher than that of the general purpose stage.

Op Amp Specifications

There are several nonideal effects in the op amp that detract from its overall performance. Mismatching of devices in the input differential pair, required bias currents, and junction voltage temperature effects can degrade the performance. These effects are described in terms of the following speciﬁcations. The diagram of Figure 23.23 is used to deﬁne various terms used in these deﬁnitions.

Input offset voltage (VOS) Mismatch of the transistors in the differential input stage leads to a ﬁnite output DC voltage when both inputs are shorted to ground. This ﬁnite output voltage is called the output offset voltage. A slight voltage mismatch in the differential pair is ampliﬁed by succeeding stages to create a larger voltage at the output. Inaccurate biasing of later stages also contribute to the output offset. Inaccuracies in later stages are ampliﬁed by smaller factors than are early stage inaccuracies.

The input offset voltage is the voltage that must be applied across the differential input terminals to cause the output voltage of the op amp to equal zero. Theoretically, this voltage could be found by measuring the output voltage when the input terminals are shorted, then dividing this value by the gain of the op amp. In practice, this may not be possible as the gain may not be known or the output offset may exceed the size of the active region. The value of VOS is typically a few millivolts for monolithic or IC op amps.

Input offset voltage drift (TCVOS): Temperature changes affect certain parameters of the transistors, leading to a drift in the output DC offset voltage with temperature. In BJT devices, the voltage across the base-to-emitter junction for a constant emitter current drops by ~2 mV/°C. Small drifts of voltage in early stages will be ampliﬁed by following stages to produce relatively large drifts in output voltage. Because the output DC signal may not exist within the active region of the op amp, the drift is again referred to the input.

The input offset voltage drift is deﬁned as the change in VOS for a 1°C change in temperature (near room temperature). A value of 10–20 µV/°C is typical for IC op amps.

Input bias current (IB). A BJT differential stage will require a ﬁnite amount of base current for biasing purposes. This is true even if both inputs are grounded. The input bias current of an op amp is deﬁned as the average value of bias current into each input with the output driven to zero. The two bias currents are generally slightly different so IB is

Common-mode input voltage range (CMVR). The voltage range over which the inputs can be simultaneously driven without causing deterioration of op amp performance is called the common-mode voltage range or CMVR. In most op amps, the CMVR is a few volts less than the rail-to-rail value of the power supplies. In many applications, both inputs are forced to move together due to the virtual short between the input terminals when negative feedback is used.

Common-mode rejection ratio (CMRR). The ratio of input common-mode voltage to change in input offset voltage is called the common-mode rejection range or CMRR. An equivalent deﬁnition is the ratio of differential voltage gain to common-mode voltage gain. IC op amps range from 80 to 100 dB for the CMRR. This parameter was mentioned earlier in the chapter and is a measure of the mismatch of incremental gain from each of the two inputs to output. If the incremental gains from each input to output were equal, the CMRR would be inﬁnite.

Power supply rejection ratio (PSRR). The power supply rejection ratio or PSRR is the ratio of change in the input offset voltage to a unit change in one of the power supply voltages. An op amp with two power supplies requires that a PSRR be speciﬁed for each power supply.

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