Architecture and Design Flow Optimizations for Power-Aware FPGAs:Conclusion and Future Directions

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Conclusion and Future Directions

Reducing the power consumption in FPGAs is an active research area. With efforts from various research groups both in academia and in the industry, the goal of developing a low-power FPGA that can be used in battery-powered devices looks feasible. Using some simple CAD techniques, we can reduce FPGA power by up to 20%, while more exotic techniques like dual-supply FPGAs can reduce the power by more than 50%.

In this chapter, we discussed the techniques to reduce the power consumption of the FPGA core, consisting of an array of CLBs. The modern FPGA contains other components like DSP blocks, high- speed transceivers, and embedded memory. Although low-power techniques for these components may have been proposed in other contexts, applying them to FPGAs will be crucial for a commercially successful low-power FPGA.

Recently, there has been a lot of activity in exploring alternate technologies for FPGAs, key among them being three-dimensional (3-D) die or wafer integration, and nanowire or nanotube-based technologies. 3-D integration involves stacking of multiple dies or wafers, with interlayer vias for communication among layers. This stacking helps in reducing the average wire-length in the implemented design, and therefore, is expected to consume less power than a 2-D implementation [35]. Although the total power reduces, the effective power density increases due to stacking of multiple power-dissipating layers, which makes low- power measures even more important for 3-D FPGAs. The other technology—use of nanowires or nanotubes to build FPGAs [36]—brings completely new challenges in terms of power consumption. These FPGAs are expected to be so dense (implying high-power densities) that keeping the die temperature within bounds will be a key design objective. Consequently, the importance of power as a design parameter in applications that are not battery-powered will keep growing. The thermal concerns will force the FPGA manufacturers as well as users to focus on transient power instead of energy, bringing new challenges to power-aware design. These power-aware methodologies will be crucial for the long-term success of FPGAs.

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