Architecture and Design Flow Optimizations for Power-Aware FPGAs:Power Consumption in FPGAs.

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Power Consumption in FPGAs

Power in FPGAs can be divided into dynamic and static powers. Dynamic power is expended only when there is some activity in the circuit, and consists of switching power as well as short-circuit power. Static power consists of leakage currents associated with all transistors in the FPGA, and auxiliary power that is consumed in some analog circuits that use a static current as reference. These analog circuits are used for internal clock generation, and for some IO standards. To summarize,

Architecture and Design Flow Optimizations for Power-Aware FPGAs-0087

where Nnets is the total number of nets, C(i) the load capacitance of net i, V the voltage swing of the net, and f the toggle rate.

Switching power dominates the dynamic power, and is much larger than that in ASICs. This is mainly due to a larger interconnect power. Most wires in an FPGA have got programmable switches connected to them, which are configured to implement the required connections. These switches add parasitic capacitances to the wires, which in turn increase the load capacitance of the net that uses the wire. Consequently, the switching power for most nets in an FPGA is much larger than that in ASICs. However, this is not the only reason for the large switching power. Because of limited number of wires available in the FPGA’s routing channel, not all nets are routed using the shortest possible path. Instead, some nets take a longer route because the wires needed to implement the shortest path have been assigned to another net. For example, in a timing-driven router, nets which are on the critical path follow the shortest path, whereas those on noncritical paths may take more circuitous routes.

Figure 20.3 shows the breakdown of dynamic power in a Virtex-2 FPGA when random input vectors are applied [12]. Note that the routing fabric consumes most of the power. This is not surprising, because

Architecture and Design Flow Optimizations for Power-Aware FPGAs-0088

Architecture and Design Flow Optimizations for Power-Aware FPGAs-0089

connections in an FPGA usually go through multiple switches, each of them adding some load capacitance as well as resistance to the net’s path. Even if a net does not connect through switch boxes, it is usually loaded by parasitic capacitances of the unused switches that could potentially be utilized for providing connections.

Leakage power dominates the static power, and can be further broken into active leakage—that consumed in the used portion of FPGA—and inactive leakage—that consumed in the transistors that are not used by the design. Inactive leakage is a big portion of total leakage, because for most FPGA designs, a large number of transistors remain unused. In fact, for many designs, inactive leakage is the dominant portion of total leakage.

Figure 20.4 shows the breakdown of leakage power for a Spartan-3 FPGA, which uses 90-nm process technology. Note the large contribution of the configuration SRAMs. These transistors can easily be optimized for leakage, because they do not affect the run-time performance of the FPGA. In fact, more recent FPGAs, such as Virtex-4, claim a much lower leakage power in their configuration SRAM. Since the routing fabric takes up most of the area in the FPGA, it is not surprising that the other major portion of leakage comes from the muxes used to implement programmable interconnect.

Manufacturers usually design FPGAs to support a large variety of customers, with varying demands for resources. This makes power reduction in FPGAs a very challenging task. For example, the routing channel width in a commercial FPGA is kept near maximum, so that almost all designs remain routable. Consequently, even if some users do not need such a large channel width, they pay in terms of power consumption. Recently, some FPGA manufacturers have started offering domain-specific FPGAs, in which the FPGA is optimized for a certain class of applications. Currently, this is done at a larger granularity, for example, by varying the number of DSP blocks, or the embedded memory, based on the application requirements. Such custom embedded blocks affect the performance as well as power of the FPGA. In general, a design, if implemented using custom hard-wired blocks, dissipates much less power (as less as 5–10% [13]) than if implemented using the configurable logic. Therefore, a signal-processing application will benefit both in energy and performance by using the DSP blocks available in some FPGAs.

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