Analog Circuit Simulation:Active Device Models.

Active Device Models

VLSI circuits contain active devices like transistors or diodes which act as amplifiers. These devices are normally described by a complicated set of non-linear equations. We shall consider a simple model for the bipolar transistor—the Ebers-Moll model. This model is one of the first developed, and while it is too simple for practical application, it is useful for discussion.

A schematic of the Ebers-Moll model is shown in Figure 13.5. The model contains three non-linear voltage-dependent current sources Ic , Ibf , and Ibr and two non-linear capacitances Cbe and Cbc. The current flowing in the three current sources are given by the following equations:

The voltages Vbe and Vbc are the voltages between base and emitter and the base and collector, respectively. Is, Bf and Br are three user-defined parameters which govern the DC operation of the BJT. Vt is the “thermal voltage” or kT/q, which has the numerical value of approximately 0.26 volts at room temperature. Observe that in the normal forward active mode, where Vbe > 0 and Vce < 0, Ibr and the second term in Ic vanish and the current gain of the BJT, which is defined as Ic/Ib becomes numerically equal to Bf. Likewise, in the reverse mode where Vce > 0 and Vbe < 0, the reverse gain (Ie /Ib) is equal to Br .

The two capacitances in Figure 13.5 contribute charge to the emitter, base, and collector, and this charge is given by the following equations:

Qbe contributes positive charge to the base and negative charge to the emitter. Qbc contributes positive charge to the base and negative charge to the collector. The first term in each charge expression is due to charge injected into the base from the emitter for Qbe and from the collector into the base for Qbc. Observe that the exponential terms in the charge terms are identical to the term in Ic. This is so because the injected charge is proportional to the current flowing into the transistor. The terms tf and tr are the forward and reverse transit times, respectively, and correspond to the amount of time it takes the electrons (or holes) to cross the base. The second term in the charge expression (the term with the integral) corresponds to the charge in the depletion region of the base–emitter junction for Qbe and in the base–collector junction for Qbc. Recall that the depletion width in a pn junction is a function of the applied voltage. The terms Vje and Vjc are the “built-in” potentials with units of volts for the base–emitter and base–collector junctions. The terms mc and me are the grading coefficients for the two junctions and are related to how rapidly the material changes from n-type to p-type across the junction.

This “simple” model has eleven constants Is, Bf , Br , Cje,Cjc,Me,Mc,Vje,Vjc, Tf, and Tr which must be specified by the user. Typically, these constants would be extracted from measured I-V and C-V data taken from real transistors using a fitting or optimization procedure (typically a non-linear least-squares fitting method is needed). The Ebers-Moll model has a number of shortcomings which are addressed in newer models like Gummel-Poon, Mextram, and VBIC. The Gummel-Poon model has over 40 parameters that must be adjusted to get a good fit to data in all regions of operation.

Models for MOS devices are even more complicated than the bipolar models. Modeling the MOSFET is more difficult than the bipolar transistor because it is often necessary to use a different equation for each of the four regions of operation (off, subthreshold, linear, saturation) and the drain current and capacitance are functions of three voltages (Vds, Vbs, and Vgs) rather than just two (Vbe and Vce) as in the case of the BJT. If a Newton-Raphson solver is to be used, the I-V characteristics and capacitances must be continuous and it is best if their first derivatives are continuous as well. Furthermore, MOS models contain the width (W) and length (L) of the MOSFET channel as parameters; and for the best utility the model should remain accurate for many values of W and L. This property is referred to as “scalability.” Over the years, literally hundreds of different MOS models have been developed. However, for modern VLSI devices, only three or four are commonly used today. These are the SPICE Level-3 MOS model, the HSPICE Level-28 model (which is a proprietary model developed by Meta Software), the public domain BSIM3 model developed at UC Berkeley, and MOS9 developed at Phillips. These models are supported by many of the “silicon foundries,” that is, parameters for the models are provided to chip designers by the foundries. BSIM3 has been observed to provide a good fit to measured data and its I-V curves to be smooth and continuous (thereby resulting in good simulator convergence). The main drawback of BSIM3 is that it has over 100 parameters which are related in intricate ways, making extraction of the parameter set a difficult process.

A process known as “binning” is used to provide greater accuracy. When binning is used, a different set of model parameters is used for each range of the channel length and width (L and W). An example

of this is shown in Figure 13.6. For a given type of MOSFET, 12 complete sets of model parameters are extracted and each is valid for a given range. For example, in Figure 13.6, the set represented by the number “11” would only be valid for channel lengths between 0.8 and 2.0 microns and for channel widths between 0.5 and 0.8 microns. Thus, for a typical BSIM3 model with about 60 parameters, 12 ´ 60 = 720 parameters would need to be extracted in all and this just for one type of device.

Many commercial simulators contain other types of models besides the traditional R, L, C, MOS, and BJT devices. Some simulators contain “behavioral” models which are useful for systems design or inte- gration tasks; examples of these are integrators, multipliers, summation, and LaPlace operator blocks. Some simulators are provided with libraries of prefitted models for commercially available operational amplifiers, logic chips, and discrete devices. Some programs allow “mixed-mode” simulation, which is a combination of logic simulation (which normally allows only a few discrete voltage states) and analog circuit simulation.