CMOS/BiCMOS Technology:CMOS Technology

Introduction

Silicon large-scale integrated circuits (LSIs) have progressed remarkably in the past 30 years. In particular, complementary metal oxide semiconductor (CMOS) technology has played a great role in the progress of LSIs. By the downsizing of MOS field effect transistors (FETs), the number of transistors in a chip increases, and the functionality of LSIs is improved. At the same time, the switching speed of MOSFETs and circuits increases and the operation speed of LSIs is improved.

In contrast, system-on-chip technology has come into widespread use [1], and, as a result, the LSI system requires several functions such as logic, memory, and analog functions [2]. Moreover, the LSI system sometimes needs an ultra-high-speed logic or an ultra-high-frequency analog function [3]. In some cases, bipolar-CMOS (BiCMOS) technology is very useful.

In Section 2.2, we focus on CMOS technology, which is the major LSI process technology, including embedded memory technology. In Section 2.3, we describe BiCMOS technology. Finally, we introduce the recent process issues.

CMOS Technology

Device Structure and Basic Fabrication Process Steps

Complementary MOS (CMOS) was first proposed by Wanlass and Sah in 1963 [4]. Although the CMOS process is more complex than the NMOS process, it provides both n-channel (NMOS) and p-channel (PMOS) transistors on the same chip and CMOS circuits can achieve lower power consumption. Con- sequently, the CMOS process has been widely used as an LSI fabrication process.

Figure 2.1 shows the structure of a CMOS device. Each “FET” consists of gate electrode, source, drain and channel, and gate bias controls carrier flow from source to drain through channel layer.

Figure 2.2 shows the basic fabrication process flow. The first process step is the formation of p tub and n tub (twin tub or twin well) in silicon substrate. Because CMOS has two types of FETs, NMOS is formed in p tub and PMOS in n tub.

The isolation process is the formation of field oxide to separate each MOSFET active area in the same tub. After that, impurity is doped into the channel region to adjust the threshold voltage, Vth, for each type of FET. Gate insulator layer, usually silicon dioxide (SiO2), is grown by thermal oxidation, because the interstate density between SiO2 and silicon substrate is small. Polysilicon is deposited as gate electrode material and gate electrode is patterned by reactive ion etching (RIE).

Gate length, Lg, is the critical dimension, because Lg determines the performance of MOSFETs and it should be small to improve the device performance. Impurity is doped in source and drain regions of MOSFETs by ion implantation. In this process step, gate electrodes act as a self-aligned mask to cover channel layers. After that, thermal annealing is carried out to activate the impurity of diffused layers.

In the case of high-speed LSI, the self-aligned silicide (salicide) process is applied for the gate electrode and source and drain diffused layers to reduce parasitic resistance. Finally, the metallization process is carried out to form interconnect layers.

Key Process Steps in Device Fabrication

Starting Material

Almost all silicon crystals for LSI applications are prepared by the Czochralski crystal growth method [5], because it is advantageous for formation of large wafers. (100) orientation wafers are usually used for MOS devices, because their interstate trap density is smaller than those of (111) and (110) orientations [6]. The light doping in the substrate is convenient for the diffusion of tub and reduces the parasitic capacitance

between the silicon substrate and tub region. As a starting material, lightly doped (~1015 atoms/cm3) p-type substrate is generally used.

Tub Formation

Figure 2.3 shows the tub structures, which are classified into six types: p tub, n tub, twin tub [7], triple tub, twin tub with buried p+ and n+ layers, and twin tub on p-epi/p+ substrate. In the case of the p tub process, NMOS is formed in p diffusion (p tub) in the n substrate, as shown in Figure 2.3(a). The p tub is formed by implantation and diffusion into n substrate at a concentration that is high enough to over- compensate the n substrate.

The other approach is to use an n tub [8]. As shown in Figure 2.3(b), NMOS is formed in the p substrate. Figure 2.3(c) shows the twin-tub structure [7] that uses two separate tubs implanted into the silicon substrate. In this case, doping profiles in each tub region can be controlled independently, and thus neither type of device suffers from excess doping effect.

In some cases, such as mixed-signal LSIs, deep n tub layer is sometimes formed optionally, as shown in Figure 2.3(d), to prevent the cross-talk noise between digital and analog circuits. In this structure, both n and p tubs are electrically isolated from the substrate and other tubs on the substrate.

To realize high packing density, tub design rule should be shrunk; however, an undesirable mechanism, the well-known latch-up, might occur.

Latch-up, i.e., the flow of high current between VDD and VSS, is caused by parasitic lateral pnp bipolar junction transistor (L-BJT) and vertical npn bipolar junction transistor (V-BJT) actions [9] as shown in Figure 2.3(a), and it sometimes destroys the functions of LSIs. The collectors of each of these bipolar junction transistors feed each others’ bases and together make up a pnpn thyristor structure. To prevent latch-up, it is important to reduce the current gain, hFE, of these parasitic bipolar junction transistors, and the doping concentration of tub region should be higher. As a result, device performance might be suppressed because of large junction capacitances.

To avoid this problem, several techniques have been proposed, such as p+ or n+ buried layer under p tub [10] as shown in Figure 2.3(e), the use of high-dose, high-energy boron p tub implants [11,12],

and the shunt resistance for emitter–base junctions of parasitic bipolar junction transistors [9,13,14]. It is also effective to provide many well contacts to stabilize the well potential and hence to suppress the latch-up. Recently, substrate with p epitaxial silicon on p+ substrate, as shown in Figure 2.3(f), is also used to stabilize the potential for high-speed logic LSIs [15].

Isolation

Local oxidation of silicon (LOCOS) [16] is a widely used isolation process, because this technique can allow channel-stop layers to be formed self-aligned to the active transistor area. It also has the advantage of recessing about half of the field oxide below the silicon surface, which makes the surface more planar. Figure 2.4 shows the LOCOS isolation process. First, silicon nitride and pad oxide are etched for the definition of active transistor area. After channel implantation as shown in Figure 2.4(a), the field oxide is selectively grown, typically to a thickness of several hundreds of nanometers.

A disadvantage of LOCOS is that the involvement of nitrogen in the masking of silicon nitride layer sometimes causes the formation of a very thin nitride layer in the active region, and this often impedes the subsequent growth of gate oxide, thereby causing low gate breakdown voltage of the oxides. To prevent this problem, a sacrificial oxide is grown and then removed before the gate oxidation process after stripping the masking silicon nitride [17,18].

In addition, the lateral spread of field oxide (bird’s beak) [17] poses a problem regarding reduction of the distance between active transistor areas to realize high packing density. This lateral spread is suppressed by increasing the thickness of silicon nitride and decreasing the thickness of pad oxide. However, there is a trade-off with the generation of dislocation of silicon.

Recently, shallow trench isolation (STI) [19] has become a major isolation process for advanced CMOS devices. Figure 2.5 shows the process flow of STI. After digging the trench into the substrate by RIE as shown in Figure 2.5(a), the trench is filled with an insulator such as silicon dioxide as shown in Figure 2.5(b). Finally, by planarization with chemical mechanical polishing (CMP) [20], filling material on active transistor area is removed, as shown in Figure 2.5(c).

STI is a useful technique for downsizing not only the distance between active areas but also the active region itself. However, the mechanical stress problem [21] still remains, and several methods have been proposed [22] to deal with it.

Channel Doping

To adjust the threshold voltage of MOSFETs, Vth, to that required by a circuit design, the channel doping process is usually required. The doping is carried out by ion implantation usually through a thin

dummy oxide film (10 to 30 nm) thermally grown on the substrate to protect the surface from contamination, as shown in Figure 2.6. This dummy oxide layer is removed prior to the gate oxidation. Figure 2.7 shows typical CMOS structure with channel doping. In this case, n+ polysilicon gate electrodes are used for both n- and p-MOSFETs and thus, this type of CMOS is called single-gate CMOS. The role of the channel doping is to enhance or raise the threshold voltage of n-MOSFETs. It is desirable that concentration of p tub is kept lower to reduce the junction capacitance of source and drain. Thus, channel doping of p-type impurity—boron—is required. Drain-to-source leakage current in short-channel MOSFETs flows in a deeper path as shown in Figure 2.8—this is called short-channel effects. Thus, heavy doping of the deeper region is effective for suppressing the short-channel effect. This doping is called deep-ion implantation.

In the case of p-MOSFET with n+ polysilicon gate electrode, the threshold voltage becomes too high in the negative direction if there is no channel doping. To adjust the threshold voltage, ultra-shallow p-doped region is formed by the channel implantation of boron. This p-doped layer is often called the counter-doped layer or buried channel layer, and p-MOSFETs with this structure are called buried- channel MOSFETs. (In contrast, MOSFETs without buried channel layer are called surface-channel MOSFETs. n-MOSFETs in this case are the surface-channel MOSFETs.) In the buried-channel case, the short-channel effect is more severe, and thus, deep implantation of n-type impurity such as arsenic or phosphorus is necessary to suppress them.

In deep submicron gate length CMOS, it is difficult to suppress the short-channel effect [23], and thus, p+ polysilicon electrode is used for p-MOSFETs as shown in Figure 2.9. For n-MOSFETs, n+ polysilicon electrode is used. Thus, this type of CMOS is called dual-gate CMOS. In the case of p+ polysilicon p-MOSFET, the threshold voltage becomes close to 0 V because of the difference in work function between n- and p-polysilicon gate electrodes [24–26], and thus, buried layer is not required. Instead, n-type impurity channel doping such as arsenic is required to raise the threshold voltage slightly in the negative direction.

Impurity redistribution during high-temperature LSI manufacturing processes sometimes makes channel profile broader, which causes short-channel effect. To suppress the redistribution, dopant with lower diffusion constant, such as indium, is used instead of boron.

For the purpose of realizing a high-performance transistor, it is important to reduce junction capacitance. To realize lower junction capacitance, a localized diffused channel structure [27,28], as shown in Figure 2.10, is proposed. Since the channel layer exists only around the gate electrode, junction capacitances of source and drain are reduced significantly.

Gate Insulator

Gate dielectric determines several important properties of MOSFETs and thus, uniformity in its thickness, low defect density of the film, low fixed charge and interface state density at the dielectric and silicon interface, small roughness at the interface, high reliability of time-dependent dielectric breakdown (TDDB) and hot-carrier-induced degradation, and high resistivity to boron penetration (explained in this section) are required. As a consequence of the downsizing of MOSFET, the thickness of gate dielectric has become thinner. Generally, the thickness of gate oxide is 7–8 nm for 0.4 µm gate length MOSFETs and 5–6 nm for 0.25 µm gate length MOSFETs.

Silicon dioxide is commonly used for gate dielectrics, which are formed by several methods, such as dry O2 oxidation and wet or steam (H2O) oxidation [29]. The steam is produced by the reaction of H2 and O2 ambient in the furnace. Recently, H2O oxidation has been widely used for gate oxidation because of good controllability of oxide thickness and high reliability.

In the case of dual-gate CMOS structure as shown in Figure 2.9, boron penetration from p+ gate electrode to channel region through gate silicon dioxide, which is described in the following section, is a problem. To prevent this problem, oxynitride has been used as gate dielectric material [30,31]. In general, oxynitride gate dielectric is formed by the annealing process in NH3, NO (or N2O) after silicon oxidation, or by direct oxinitridation of silicon in NO (or N2O) ambient. Figure 2.11 shows the typical nitrogen profile of oxynitride gate dielectric. Recently, remote plasma nitridation [32,33] has been much studied and it is reported that oxynitride gate dielectric grown by the remote plasma method showed better quality and reliability than that grown by the silicon nitridation method.

In the sub-quarter-micron CMOS device regime, gate oxide thickness is close to the limitation of tunneling current flow, around 3 nm thickness. To prevent tunneling current, high dielectric constant, κ, materials, such as Si3N4 [34] and Ta2O5 [35,36], are proposed instead of silicon dioxide. In these cases, the thickness of gate insulator can be kept at a relatively thick value, because high-κ insulator realizes high gate capacitance, and thus better driving capability.

Gate Electrode

Heavily doped polysilicon has been widely used for gate electrode because of its stability to high-temperature LSI fabrication processing. To reduce the resistance of gate electrode which contributes significantly to RC delay time, silicides of refractory metals have been put on the polysilicon electrode [37,38]. Polycide [38], the technique of combining a refractory metal silicide on top of doped polysilicon, has the advantage of preserving the good electric and physical properties at the interface between polysilicon and gate oxide while, at the same time, the sheet resistance of gate electrode is reduced significantly.

For doping the gate polysilicon, ion implantation is usually employed. In the case of heavy doping, dopant penetration from boron-doped polysilicon to the silicon substrate channel region though the gate oxide occurs in the high-temperature LSI fabrication processes as shown in Figure 2.12. (In contrast, usually, penetration of the n-type dopant, such as phosphorus or arsenic does not occur.) When the doping of impurities in the polysilicon is not sufficient, the depletion of gate electrode occurs as shown in Figure 2.13, resulting in significant decrease in the drive capability of transistor as shown in Figure 2.14 [39]. There is a trade-off between the boron penetration and the gate electrode depletion, and so thermal process optimization is required [40]. Recently, polysilicon germanium (SiGe) gate FET is demonstrated to prevent this depletion phenomenon of gate electrode [41].

Gate length is one of most important dimensions defining MOSFET performance, and thus the lithography process for gate electrode patterning requires high-resolution technology.

In the case of light-wave source, g-line (wavelength 436 nm) and i-line (365 nm) of mercury lamp were popular methods. Recently, a higher-resolution process, excimer laser lithography, has been used. In the excimer laser process, KrF (248 nm) [42] and ArF (193 nm) [43] have been proposed and developed. For around 0.25 µm gate length electrode, the KrF excimer laser process is widely used in the production of devices. In addition, electron-beam [44–46] and x-ray [47] lithography techniques are being studied for sub-0.1 µm lithography.

For etching of gate polysilicon, a high-selectivity RIE process is required for selecting polysilicon from SiO2, because the gate dielectric beneath the polysilicon is a very thin film in the case of recent devices.

Source/Drain Formation

Source and drain diffused layers are formed by the ion implantation process. As a consequence of transistor downsizing, at the drain edge (interface of channel region and drain) where reverse-biased pn junctions exist, higher electrical field has been observed. As a result, carriers across these junctions are suddenly accelerated and become hot carriers, which create a serious reliability problem for MOSFET [48].

(c) Sidewall spacer formation. (d) Source/drain implantation.

To prevent the hot carrier problem, the lightly doped drain (LDD) structure is proposed [49]. The LDD process flow is shown in Figure 2.15. After gate electrode formation, ion implantation is carried out to make extension layers, and the gate electrode plays the role of self-aligned mask which covers channel layer, as shown in Figure 2.15(b). In general, arsenic is doped for n-type extension of NMOS, and BF2 for p-type extension of PMOS. To prevent the short-channel effect, impurity profile of the extension must be very shallow. Although shallow extension can be realized by ion implantation with low dose, the resistivity of extension layers becomes high, and thus, MOSFET characteristics degrade. Hence, it is very difficult to meet these two requirements. Also, impurities diffusion in this extension affects the short-channel effect significantly. Thus, it is necessary to minimize the thermal process after forming extension.

Insulating film, such as Si3N4 or SiO2, is deposited by the chemical vapor deposition method. Then, etching back RIE treatment is performed on the whole wafer, and, as a result, the insulating film remains only at the gate electrode side as shown in Figure 2.15(c). This remaining film is called a sidewall spacer. This spacer works as a self-aligned mask for deep source/drain n+ and p+ doping, as shown in Figure 2.15(d). In general, arsenic is doped for deep source/drain of NMOSFET, and BF2 for PMOSFET. In the dual-gate CMOS process, gate polysilicon is also doped in this process step to prevent gate electrode depletion.

After that, to make doped impurities activate electrically and to recover from implantation damage, an annealing process, such as rapid thermal annealing (RTA), is carried out.

According to the MOSFET scaling law, when gate length and other dimensions are shrunk by factor k, the diffusion depth also needs to be shrunk by 1/k. Hence, the diffusion depth of the extension part is required to be especially shallow.

Several methods have been proposed for forming an ultra-shallow junction. For example, very low accelerating voltage implantation, the plasma doping method [50], and implantation of heavy molecules, such as B10H14 for p-type extension [51], are being studied.

Salicide Technique

As the vertical dimension of transistors is reduced with device downscaling, an increase is seen in sheet resistance; both of the diffused layers, such as source and drain, and the polysilicon films, such as the gate electrode. This is becoming a serious problem in the high-speed operation of integrated circuits.

Figure 2.16 shows the dependence of the propagation delay time (tpd) of CMOS inverters on the scaling factor, k, or gate length [52]. These results were obtained by simulations in which two cases were considered. First is the case in which source and drain contacts with the metal line were made at the edge of the diffused layers, as illustrated in the figure inset. In an actual LSI layout, it often happens that the metal contact to the source or drain can be made only to a portion of the diffused layers, since many other signal or power lines cross the diffused layers. The other case is that in which the source and drain contacts cover the entire area of the source and drain layers, thus reducing diffused line resistance. It is clear that without a technique to reduce the diffused line resistance, tpd values cannot keep falling as transistor size is reduced; they will saturate at gate lengths of around a quarter micron.

To prevent this problem—the high resistance of shallow diffused layers and thin polysilicon films—self- aligned silicide (salicide) structures for the source, drain, and gate have been proposed, as shown in Figure 2.17 [53–55].

First, a metal film such as Ti or Co is deposited on the surface of the MOSFET after the formation of the polysilicon gate electrode, gate sidewall, and source and drain diffused layers, as shown in Figure 2.17(b). The film is then annealed by RTA in an inert ambient. During the annealing process, the areas of metal film in direct contact with the silicon layer—that is, the source, drain, and gate electrodes—are selectively converted into the silicide and other areas remain metal, as show in Figure 2.17(c).

(b) Metal deposition. (c) Silicidation by thermal annealing. (d) Removal of non-reactive metal.

The remaining metal can be etched off with an acid solution such as H2O2 + H2SO4, leaving the silicide self-aligned with the source, drain, and gate electrode, as shown in Figure 2.17(d).

When the salicide process first came into use, furnace annealing was the most popular heat-treatment process [53–55]; however, RTA [56–58] replaced furnace annealing early on, because it is difficult to prevent small amounts of oxidant entering through the furnace opening, and these degrade the silicide film significantly since silicide metals are easily oxidized. In contrast, RTA reduces this oxidation problem significantly, resulting in reduced deterioration of the film and consequently of its resistance.

For sub-half-micron gate length FETs, TiSi2 [56–58] is widely used as a silicide in LSI applications. However, in the case of ultra-small geometry MOSFETs for VLSI, use of TiSi2 is subject to several problems. When the TiSi2 is made thick, a large amount of silicon is consumed during silicidation, and this should result in problems of junction leakage at the source or drain. On the contrary, if a thin layer of TiSi2 is chosen, agglomeration of the film occurs [59] at higher silicidation temperatures.

However, CoSi2 [60] and NiSi [61] have a large silicidation temperature window for low sheet resistance;

hence, it is expected to be widely used as silicidation material for advanced VLSI applications [62].

Interconnect and Metallization

Aluminum is widely used as a wiring metal for VLSI. However, in the case of downsized CMOS, electro- migration (EM) [63] and stress migration (SM) [64] become serious problems. To prevent these prob- lems, Al–Cu (typically ~0.5 wt% Cu) [65] is a useful wiring material. In addition, ultra-shallow junction

for downsized CMOS sometimes needs barrier metal [65] such as TiN, between metal and silicon, to prevent junction leakage current.

Figure 2.18 shows a cross-sectional view of a multilayer metallization structure. As a consequence of CMOS downscaling, contact or via aspect ratio becomes larger, and, as a result, filling of contact or via is not sufficient. Hence, new filling techniques, such as W-plug [66,67], are widely used.

In addition, considering both reliability and low resistivity, Cu [68] is a useful wiring material. In the case of Cu interconnects, metal thickness can be reduced for realizing the same interconnect resistance of alumi- num case. The reduction of the metal thickness is useful for reducing the capacitance between the dense interconnect wires, resulting in the high-speed operation of the circuit. To reduce RC delay of wire in CMOS LSI, not only the wiring material but also the interlayer material is important. In particular, low dielectric constant, κ, film is widely studied [69]. Table 2.1 shows various low-κ films for ultra-small geometry devices [70]. Also, several low-κ materials are demonstrated for sub-50 nm node processes [71–74].

In the case of Cu wiring, the dual-damascene process [75–77] is being widely used, because it is difficult to realize fine Cu pattern by RIE. Figure 2.19 shows the process flow of Cu dual-damascene metallization. After deposition of dielectric interlayer as shown in Figure 2.19(a), trenches for via contact and wiring area are formed as shown in Figure 2.19(b). By using electroplating method, Cu film was deposited, and then the CMP process [78] is carried out for planarization as shown in Figure 2.19(c). It should be noted that a barrier metal, such as TiN, is essential between Cu and interlayer to prevent Cu diffusion into dielectric layers.

Passive Device for Analog Operation

System-on-chip technology has come into widespread use, and, as a result, the LSI system sometimes requires analog functions. In this case, analog passive devices should be integrated [79,80], as shown in Figure 2.20.

Resistors and capacitors [81] already have good performance, even for high-frequency applications. However, it is difficult to realize a high-quality inductor on a silicon chip, because of inductance loss in silicon substrate, in which the resistivity is lower than that in the compound semiconductor, such as GaAs, substrate. Relatively higher sheet resistance of aluminum wire used for high-density LSI is another problem. Recently, the quality of inductor has been improved by using thicker Al or Cu wire [82] and by optimizing substrate structure [83–87].

Embedded Memory Technology

Embedded DRAM

There has been a strong motivation to merge DRAM cell arrays and logic circuits in a single silicon chip. This approach makes it possible to realize high bandwidth between memory and logic, low power consumption, and small footprint of the chip [88]. To merge logic and DRAM into a single chip, it is necessary to establish process integration for the embedded DRAM. Figure 2.21 shows the typical structure of embedded DRAM. However, the logic process and DRAM process are not compatible with each other. There are many variations and options in constructing the consistent process integration for the embedded DRAM.

Trench Capacitor Cell Versus Stacked Capacitor Cell.

There are two types of DRAM cell structure: stacked capacitor cell [89–94] and trench capacitor cell [95,96].

In trench cell technology, the cell capacitor process is completed before gate oxidation. Therefore, there is no thermal process due to cell capacitor formation after the MOSFET formation. Another advantage of the trench cell is that there is little height difference between cell array region and peripheral circuit region [97–100].

In the stacked capacitor cell, the height difference causes high aspect ratio contact holes and difficulty in the planarization process after the cell formation. The MOSFET formation steps are followed by the stacked capacitor formation steps, which include high-temperature process steps such as storage node insulator (SiO2/Si3N4) formation and Si3N4 deposition for the self-aligned contact formation. The salicide process for the source and drain of the MOSFETs should be carefully designed to endure the high- temperature process steps. Recently, high-permittivity film for capacitor insulator, such as Ta2O5 and BST, has been developed for commodity DRAM and embedded DRAM. The process temperature for Ta2O5 and BST is lower than that for SiO2/Si3N4; this means the process compatibility is better with such high- permittivity film [101–103].

MOSFET Structure.

The MOSFET structure in DRAMs is different from that in logic ULSIs. In recent DRAMs, the gate is covered with Si3N4 for self-aligned contact process steps in the bit-line contact formation. It is very

difficult to apply the salicide process to the gate, source, and drain at the same time. A solution to the problem is to apply the salicide process to the source and drain only. A comparison of the MOSFET structures is shown in Figure 2.22. Tsukamoto et al. [89] proposed another approach, namely the use of W-bit line layer as local interconnect in the logic portion.

Gate Oxide Thickness.

Generally, DRAM gate oxide thickness is greater than that of the logic VLSIs. This is because maximum voltage of the transfer gate in the DRAM cells is higher than VCC, the power supply voltage. In the logic VLSI, the maximum gate voltage is equal to VCC in most cases. To keep up with the MOSFET performance in logic VLSIs, the oxide thickness of the embedded DRAMs needs to be scaled down further than in the DRAM case. To do so, highly reliable gate oxide and new circuit scheme in the word line biasing, such as applying negative voltage to the cell transfer gate, is required.

Another approach is to use thick gate oxide in the DRAM cell and thin gate oxide in the logic [104].

Fabrication Cost Per Wafer.

The conventional logic VLSIs do not need the process steps for the DRAM cell formation. In contrast, most of the DRAMs use only two layers of aluminum. This raises wafer cost of the embedded DRAMs. Embedded DRAM chips are used only if the market can absorb the additional wafer cost for some reasons: high bandwidth, lower power consumption, small footprint, flexible memory configuration, lower chip assembly cost, etc.

Next-Generation Embedded DRAM.

Process technology for the embedded DRAM with 90 or 65 nm design rules will include state-of-the-art DRAM cell array and high-performance MOSFETs in the logic circuit [105,106]. The embedded DRAM could be a technology driver because the embedded DRAM contains most of the key process steps for DRAM and logic VLSIs.

Recently, the importance of embedded flash technology has been increasing and logic chips with non- volatile functions have become indispensable for meeting various market requirements.

Key issues in the selection of an embedded flash cell [108] are (1) tunnel-oxide reliability (damage- less program/erase(P/E) mechanism), (2) process and transistor compatibility with CMOS logic, (3) fast read with low VCC , (4) low power (especially in P/E), (5) simple control circuits, (6) fast program speed, and (7) cell size. This ordering largely depends on target device specification and memory density, and, in general, is different from that of high-density stand-alone memories. NOR-type flash is essential and EEPROM functionality is also required on the same chip [109]. Figure 2.23 shows the typical device structure of NOR-type flash memory with logic device.

To realize high-performance embedded flash chips, at least three kinds of gate insulators are required beyond the 0.25 µm regime; to form flash tunnel oxide, CMOS gate oxide, high-voltage transistor gate oxide, and I/O transistor gate oxide. Flash cells are usually made by the stacked gate process. Therefore, it is difficult to achieve less than 150% of the cost of pure logic devices.

The two different approaches to realize embedded flash chips are (a) memory-based and (b) logic- based, as shown in Figure 2.24.

(a) is advantageous in that it exploits established flash reliability and yield guaranteed by memory mass production lines, but is disadvantageous for realizing high-performance CMOS transistors due to the additional flash process thermal budget. On the contrary, (b) can use fully CMOS-compatible transistors as they are, but, due to the lack of dedicated mass production lines, great efforts are required to establish flash cell reliability and performance. Historically, (a) has been adopted, but (b) has become more important recently. In general, the number of additional masks required to embed flash cell into logic chips ranges from 4 to 9.

For high-density embedded flash chips, one transistor stack gate cell using channel hot electron programming and channel FN tunneling erasing will be mainstream. For medium- or low-density high- speed embedded flash chips, two transistors will be important in the case of using the low-power P/E method. From the reliability point of view, p-channel cell using band-to-band tunneling induced electron injection [111] and channel FN tunneling ejection are promising since page-programmable EEPROM can also be realized by this mechanism [108].