CMOS Amplifier Design:Biasing Circuits
Biasing Circuits
A fundamental component of any CMOS amplifier is a biasing circuit. This section presents important design topologies and considerations used in the design of CMOS biasing circuits. We begin this section with a discussion of current mirrors.
The Current Mirror
The basic CMOS current mirror is shown in Figure 22.6. For the moment, we will not concern ourselves with the implementation of IREF . By tying M1’s gate to its drain, we set VGS at a value given by
For most design applications, the term under the square root is set to a few hundred millivolts or less. Because M2’s gate-source voltage, and thus its drain current (IOUT), is set by IREF , we say that M2 mirrors the current in M1. If M2’s b is different than M1’s, we can relate the currents by
Notice that we have neglected the finite output resistance of the MOSFETs in this equation. If we include the effects of finite output resistance, and assume M1 and M2 are sized the same, we see from Figure 22.6 that the only time IREF and IOUT are equal is when VGS = VOUT = VDS2.
Design Example
Design a 100-mA current sink and a 200-mA current source assuming that you are designing with a 0.5-mm CMOS process with KPn = 150 mA/V2, KPp = 50 mA/V2, VTHN = 0.8 V, and VTHP = 0.9 V. Assume l was empirically determined (or determined from simulations) to be 0.05 V–1 with L = 2.0 mm. Assume that an IREF of 50 mA is available for the design. Determine the output resistance of the current source/sink and the minimum voltage across the current source/sink.
The schematic of the design is shown in Figure 22.7. If we design so that that term (2IREF )/ b1 is 300 mV, the width of M1, W1, is 15 mm (KPn = 150 mA/V2, L = 2 mm). The MOSFET, M1, has a gatesource voltage 300 mV in excess of the threshold voltage, or, in other words, the MOSFET VGS is 1.1 V.
For M2 and M3 to sink 100 mA (twice the current in M1), we simply increase their widths to 30 mm for the same VGS bias supplied by M1. Note the minimum voltage required across M3, VDS3, in order to keep M3 out of the triode region (VDS3 VGS – VTHN), is simply the excess gate voltage, (2I REF ) / b1, or, for this example, 300 mV. (Note: simply put, 300 mV is the minimum voltage on the drain of M3 required to keep it in the saturation region.) Increasing the widths of the MOSFETs lowers the minimum voltage required across the MOSFETs (lowers the excess gate voltage) so they remain in saturation at the price of increased layout area. Also, differences in MOSFET threshold voltage become more significant, affecting the matching between devices. Note that the output resistance of M3 is simply.
The purpose of M2 should be obvious at this point; it provides a 100-mA bias for the p-channel current mirror M4/M5. Again, if we set M4’s excess gate voltage to 300 mV (so that the VSG of the p-channel MOSFET is 1.2 V), the width of M4 can be calculated (assuming that L is 2 mm and KPp = 50 mA/V2) to be 45 mm (or a factor of 3 times the n-channel width due to the differences in the transconductance parameters of the MOSFETs). Since the design required a current source of 200 mA, we increase the width of the p-channel, M5, to 90 mm (so that it mirrors twice the current that flows in M4). The output resistance of the current source, M5, is 100 kW, while the maximum voltage on the drain of M5 is 3 V (in order to keep M5 in saturation.)
Layout of Current Mirrors
In order to get the best matching between devices, we need to lay the MOSFETs out so that differences in the mirrored MOSFETs’ widths and lengths are minimized. Figure 22.8 shows the layout of the M1 (15/2) and M2 (30/2) MOSFETs of Figure 22.7. Notice how, instead of laying M2 out in a fashion similar to M1 (i.e., a single poly over active strip), we split M2 into two separate MOSFETs that have the same shape as M1.
The matching between current mirrors can also be improved using a common-centroid layout (Figure 22.9). Parameters such as the threshold voltage and KP in practice can have a somewhat linear change with position on the wafer. This may be the result of varying temperature on the top of the wafer during processing, or fluctuations in implant dose with position. If we lay MOSFETs M2 and M1 out as shown in Figure 22.9(a) (which is the same way they were laid out in Figure 22.8), M1 has a “weight” of 1 while M2 has a weight of 5. These numbers may correspond to the threshold voltages of three individual MOSFETs with numerical values 0.81, 0.82, and 0.83 V. By using the layout shown in Figure 22.9(b), M1’s or M2’s average weight is 2. In other words, using the threshold voltages as an example, M1’s threshold voltage is 0.82 V while the average of M2’s threshold voltage is also 0.82 V. Similar discussions
can be made if the transconductance parameters vary with position. Figure 22.9(c) shows how three devices can be matched using a common-centroid layout (M2 and M1 are the same size while M3 is 4 times their size.) A good exercise at this point is to modify the layout of Figure 22.9(c) so that M2 is twice the size of M1 and one half the size of M3.
The Cascode Current Mirror
We saw that in order to improve the matching between the two currents in the basic current mirror of Figure 22.6, we needed to force the drain-source voltage of M2 to be the same as the drain-source voltage of M1 (which is also VGS in Figure 22.6). This can be accomplished using the cascode connection of MOSFETs shown in Figure 22.10. The term “cascode” comes from the days of vacuum tube design where a cascade of a common-cathode amplifier driving a common-grid amplifier was used to increase the speed and gain of an overall amplifier design.
Using the cascode configuration results in higher output resistance and thus better matching. For the following discussion, we will assume that M1 and M3 are the same size, as are M2 and M4. Again, remember that M1 and M2 form a current mirror and operate in the same way as previously discussed. The addition of M3 and M4 helps force the drain-source voltages of M1/M2 to the same value. The minimum VOUT allowable, in order to keep M4 out of the triode region, across the current mirror increases to
The output resistance of the cascode configuration can be derived with the circuit model of Figure 22.11.
Here, we assume that the gates of M4 and M2 are at fixed DC potentials (which are set by IREF flowing through M1/M3). Since the source of M2 is held at ground, we know that the AC component of vgs2 is 0. Therefore, we can replace M2 with a small-signal resistance ro = (1/lIOUT). To determine the output resistance of the cascode current mirror, we apply an AC test voltage, vtest, and measure the AC test current that flows into the drain of M4. Ideally, only the DC component will flow through vtest. We can write the AC gate-source voltage of M4 as vgs4 = –itest · ro. The drain current of M4 is then gm4vgs4 = –itest · gm4ro while the current through the small-signal output resistance of M4, ro, is (vtest – (–itestro))/ro. Combining
The cascode current source output resistance is gmro (the open-circuit voltage gain of a MOSFET) times larger than ro (the simple current mirror output resistance.) The main drawback of the cascode config- uration is the increase in the minimum required voltage across the current sink in order for all MOSFETs to remain in the saturation region of operation.
Low-Voltage Cascode Current Mirror
If we look at the cascode current mirror of Figure 22.10, we see that the drain of M2 is held at the same potential as the drain of M1, that is, VGS or (2IREF)/ b+ VTHN . We know that the voltage on the drain of M2 can be as low as (2IREF)/ b before it starts to enter the triode region. Knowing this, consider the wide-swing current mirror shown in Figure 22.12. Here, “wide-swing” means the minimum voltage across the current mirror is 2 (2IREF)/ b , the sum of the excess gate voltages of M2 and M4.
To understand the operation of this circuit, assume that M1 through M4 have the same W/L ratio (their bs are all equal). We know that the VGS of M1 and M2 is (2IREF)/ VTH . It is desirable to b+ N keep M2’s drain at (2IREF)/ b for wide-swing operation. This means, since M3/M4 are the same size
as M1/M2, the gate voltage of M3/M4 must be VGS + (2IREF)/ b or 2 (2IREF)/ b+ VTHN. By sizing M5’s channel width so that it is one fourth of the size of the other transistor widths and forcing IREF through the diode connected M5, we can generate this voltage. We should point out that the size (its W/L ratio) of M5 can be further decreased, say to 1/5, in order to keep M1/M2 from entering the triode region (and the output resistance from decreasing). The cost is an increase in the minimum allowable voltage across M2/M4, that is, VOUT .
Simple Current Mirror Biasing Circuits
Figure 22.13 shows two simple circuits useful for generating the reference current, IREF , used in the current mirrors discussed in the previous section. The circuit shown in Figure 22.13(a) uses a simple resistor with a gate-drain connected MOSFET to generate a reference current. Note how, by adding MOSFETs mirroring the current in M1 or M2, we can generate any multiple of IREF needed. The reference current, of Figure 22.13(a), can be determined by solving
Notice in both equations above that the reference current is a function of the power supply voltage. Fluctuations, as a result of power supply noise, in VDD directly affect the bias currents. In the next section, we will present a method for generating currents that reduces the currents’ sensitivity to changes in VDD.
Temperature Dependence of Resistors and MOSFETS
Figure 22.14 shows how a resistor changes with temperature, assuming a linear dependence. The temperature coefficient is used to relate the value of a resistor at room temperature, or some known temperature T0, to the value at a different temperature. This relationship can be written as
where TCR is the temperature coefficient of the resistor ppm/°C (parts per million, a multiplier of 10–6, per degree C). Typical values for TCRs for n-well, n+, p+, and poly resistors are 2000, 500, 750, and 100 ppm/°C, respectively.
Figure 22.15 shows how the drain current of a MOSFET changes with temperature. At low gate-source voltages, the drain current increases with increasing temperature. This is a result of the threshold voltage decreasing with increasing temperature which dominates the I-V characteristics of the MOSFET. The temperature coefficient of the threshold voltage (NMOS or PMOS), TCVTH, is generally around –3000 ppm/°C. We can relate the threshold voltage to temperature using
around 1.8 V, for a typical CMOS process, the drain current does not change with temperature. The mobility can be related to temperature by
The Self-Biased Beta Multiplier Current Reference Figure 22.16 shows the self-biased beta multiplier current reference. This circuit employs positive feed- back, with a gain less than one, to reduce the sensitivity of the reference current to power supply changes. MOSFET M2 is made K times wider than MOSFET M1 (in other words, b2 = Kb1; hence, the name beta
Because of the possibility of zero current flowing in the reference, a start-up circuit should always be used when using the beta multiplier. The purpose of the start-up circuit is to ensure that point B is avoided. When designed properly, the start-up circuit [Figure 22.17(b)] does not affect the beta multiplier operation when IREF is non-zero (M3 is off when operating at point A).
A Comment About Stability
Since the beta multiplier employs positive feedback, it is possible that the circuit can become unstable and oscillate. However, with the inclusion of the resistor in series with the source of M2, the gain around the loop, from the gate of M2 to the drain/gate of M1, with the loop broken between the gates of M1 and M2, is less than one, keeping the reference stable. Adding a large capacitance across R, however, can increase the loop gain to the point of instability. This situation could easily occur if R is bonded out to externally set the current.
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