Positive/negative amplifier

By -

Positive/negative amplifier

The circuit below has unity gain with switchable sign. When the contact is open the amplifier is effectively a voltage follower (V = Vinl· When the switch is closed the amplifier acts as a simple inverting circuit, again with unity gain (V = - Vinl· The state of the switch determines the sign of the gain.

image

Although this shows a mechanical switch, in practice a CMOS analog switch (such as the 4016) allows the circuit to be switched at high speed with logic level signals. The circuit is useful in instrumentation circuits.

Current/voltage conversion

Conversion between current and voltage signals is often required. A standard analog instrumentation signal, for example, uses a range of 4-20 rnA and this often has to be converted to a voltage for display purposes. Similarly, a voltage may be required to be converted to a current for use with a signal transmission system.

Where analog information has to be transmitted over long  distances, current signals are generally preferred to voltage signals as they are less affected by noise and line resistance. Circuits for conversion between voltage and current analog signals are shown.

 image

A variation on a voltage follower is shown in (a). As usual, V1 = Vin• but V 1 = lR where I is the current flowing through the load. I is therefore set by Vin and is totally independent of the load resistance  (provided the amplifier output does not saturate).

To go from a current signal to a voltage signal, (b) can be used. The current passes through a load resistance across the input of a standard differential amplifier. Voltage across the load resistance is simply lR volts; the output voltage is determined by the differential amplifier gain, as described earlier.

If both circuits are used together, with the resistors of (a) and (b) equal and the differential amplifier set for unity gain, the resulting circuit becomes a unity gain transmission link, which can be used to pass analog values through an electrically noisy area.

Ramp circuit

A circuit whose output changes at a fixed rate is shown. The output voltage follows the input voltage (albeit inverted), but the rate of change is limited. Such circuits are used to limit the acceleration of, say, electric motors, to reduce wear.

Amplifier I acts as a comparator, comparing V with Vi. The output of amplifier I is therefore saturated either positive or negative ifV doesnotequal Vi.

Amplifier 2 is an integrator, and integrates the output of amplifier

I. If the output of amplifier I is positive V ramps negative. The values of Rand C determine the ramp rate. Similarly, if the output of amplifier I is negative, V ramps positive at a fixed rate.

If Vi changes V ramps in the required direction at a fixed rate until V again equals Vi. Action of the circuit is shown in (b). When input and output are equal the output of amplifier I is nominally zero, but in practice it tends to dither about randomly. This does not affect the output.

image

Peak picker circuit

A peak picker holds the maximum value of a signal. If V; is greater than V ,the output of amplifier 1 (which acts as a comparator) goes  positive, charging C until V equals V;. As V; falls again, the voltage on the capacitor is held, and the output of amplifier I swings  negative as V; falls below V • The diode is back-biased, so there is no route for the capacitor to discharge (except through the high input impedance of amplifier 2, which is normally a FET amplifier).

image

The output voltage therefore holds the highest value of Vi. If the diode is reversed the output voltage is the lowest value of Vi. A sample and hold circuit can be formed by replacing the diode with a switch (either a physical contact or a CMOS transmission gate).

Voltage V now holds the value of V at the instant the switch was  last opened. Sample and hold circuits are used to freeze the value of  an input to a digital-to-analog converter.

Comments

Post a Comment

Popular posts from this blog

Square wave oscillators and Op-amp square wave oscillator.

By -
Image
Square wave oscillators If Fourier analysis is performed on a square wave it is found that the waveform is composed of many harmonics of the fundamental frequency. This rich harmonic content makes the square wave particularly useful as a quick test of amplifier performance. Examples of possible results are shown. The simplest way to produce a square wave is to make a sine wave oscillator in one of the ways described earlier, then feed the output to some form of squaring circuit such as a Schmitt trigger. This is the method adopted in most commercial sine/square wave generators. There are, however, several circuits for square wave oscillators and a description of the most common follows. Multivibrator Technically the multivibrator is a relaxation oscillator, working on the charging of a capacitor through a resistor. If a negative edge is applied to the circuit in (a), transistor TR 1 turns off the for time taken for the base voltage to return to 0 V. If the voltage step is
Read more

Adders:Carry Look-Ahead Adder.

By -
Image
Carry Look-Ahead Adder As previously stated, the carry, c i +1, produced at the i -th position is calculated as c i +1 = x i · y i ∨ c i ·( x i ⊕ y i ). This means that a carry is generated if both x i and y i are 1, or an incoming carry is propagated if one of x i and y i is 1 and the other is 0. Therefore, letting g i denote x i y i , we have c i +1 = g i ∨ c i p i , where p i = x i ⊕ y i . Here, g i is the formula for the carry generation condition at the i -th position, i.e., when g i is 1, a carry is generated at this position. Substituting g i –1 ∨ p i –1 c i –1 for c i , we get A carry look-ahead adder can be realized according to this expression, as illustrated in Figure 41.10 for the case of four bits [21]. According to this expression, c i +1’s are calculated at all positions in parallel. It is hard to realize an n -bit carry look-ahead adder precisely according to this expression, unless n is small, because maximum fan-in and fan-out restriction is violated at higher
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f
Read more