Dynamic Random Access Memory:DRAM Memory Cell
DRAM Memory Cell In early CMOS DRAM storage cell design, three-transistor and four-transistor cells were used in 1-Kb and 4-Kb generations. Later, a particular one-transistor cell, as shown in Figure 55.4(a), became the industry standard [5,6]. The one-transistor (1T) cell achieves smaller cell size and low cost. The cell consists of an n-channel MOSFET and a storage capacitor C s. The charge is stored in the capacitor C s and the n-channel MOSFET functions as the access transistor. The gate of the n-channel MOSFET is connected to the word-line WL and its source/drain is connected to the bit-line. The bit-line has a capacity C BL , including the parasitic load of the connected circuits. The DRAM cell stores one bit of information as the charge on the cell storage capacitor C s. Typical values for the storage capacitor C s are 30 to 50 fF. When the cell stores “1”, the capacitor is charged to V DD – V t. When the stores “0”, the capacitor is discharged to 0 V. During the READ ...
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