Logic terms and Basic logic symbols and truth tables.

By -

Logic terms

Astable Type of multivibrator circuit, producing a square wave oscillation.

Asynchroa- Operation not dependent on clock pulses. Bistable Type of multivibrator circuit. having two stable states. Buffered Capable of driving external circuits, isolated from previous stage.

Clock Source of regular voltage pulses. used to synchronise systems.

Decoder Device capable of translating a BCD input to separate control line inputs (also known as a demultiplexer).

Dual Two, twin.

Edge triggered Operation of device takes place on rising (or falling) part of input pulse.

Enable Over-ride input.

Fu-out Number of devices that can be placed in parallel on output.

nip-llop Two-state device, changes state when clocked.

Hex Six.

Latch Retains previous input state until over-ridden.

Monostable Type of multivibrator circuit. with one stable state. Multiplexer Samples many inputs in sequence, gives one output. Multivlbrator Circuit having two output states. each of which may

or may not be stable. Oscillators of astable. bistable. or monostable

types can be built with multivibrators.

Octal Eight.

One-shot Gives single output pulse of defined duration from variable input pulse.

Open collector TTL output which needs external pull-up resistor. can be used to wire OR outputs.

Parity Check bit added to data. can be odd or even parity. In odd parity sum of data Is + parity I is odd.

Propagation delay Time taken for signal to pass through a device. limits highest frequency of operation.

Quad Four.

Quiescent Stable state not driving a load.

Schmitt trigger Circuit with hysteresis.

Synchronous Operation dependent on clock pulses.

Basic logic symbols and truth tables

Logic symbols are to the Mil Std-8068 specification, as they are in more general use than those of B.S.3939. Positive logic convention used. i.e. I= high. 0 =low.

image

Medium scale integrated logic symbols and terminology

Medium scale integrated (MSI) logic elements are represented by rectangular blocks with appropriate external AND/0 R gates when necessary. A small circle at an external input means that the specific input is active Low, i.e., it produces the desired function. in conjunction with other inputs, if its voltage is the lower of the two logic levels in the system. A circle at the output indicates that when the function designated is True, the output is Low. Generally, inputs are at the top and left and outputs appear at the bottom and right of the logic symbol. An exception is the asynchronous Master

Reset in some sequential circuits which is always at the left-hand bottom corner.

image

Inputs and outputs are generally labelled with mnemonic letters. Those used in this book are listed below. Note that an active Low function labelled outside of tbe logic symbol is given a bar over tbe label, while the same function inside the symbol is labelled without the bar. When several inputs or outputs use the same letter, subscript numbers starting with zero are used in an order natural for device operation.

image

image

Comments

Post a Comment

Popular posts from this blog

Square wave oscillators and Op-amp square wave oscillator.

By -
Image
Square wave oscillators If Fourier analysis is performed on a square wave it is found that the waveform is composed of many harmonics of the fundamental frequency. This rich harmonic content makes the square wave particularly useful as a quick test of amplifier performance. Examples of possible results are shown. The simplest way to produce a square wave is to make a sine wave oscillator in one of the ways described earlier, then feed the output to some form of squaring circuit such as a Schmitt trigger. This is the method adopted in most commercial sine/square wave generators. There are, however, several circuits for square wave oscillators and a description of the most common follows. Multivibrator Technically the multivibrator is a relaxation oscillator, working on the charging of a capacitor through a resistor. If a negative edge is applied to the circuit in (a), transistor TR 1 turns off the for time taken for the base voltage to return to 0 V. If the voltage step is
Read more

Adders:Carry Look-Ahead Adder.

By -
Image
Carry Look-Ahead Adder As previously stated, the carry, c i +1, produced at the i -th position is calculated as c i +1 = x i · y i ∨ c i ·( x i ⊕ y i ). This means that a carry is generated if both x i and y i are 1, or an incoming carry is propagated if one of x i and y i is 1 and the other is 0. Therefore, letting g i denote x i y i , we have c i +1 = g i ∨ c i p i , where p i = x i ⊕ y i . Here, g i is the formula for the carry generation condition at the i -th position, i.e., when g i is 1, a carry is generated at this position. Substituting g i –1 ∨ p i –1 c i –1 for c i , we get A carry look-ahead adder can be realized according to this expression, as illustrated in Figure 41.10 for the case of four bits [21]. According to this expression, c i +1’s are calculated at all positions in parallel. It is hard to realize an n -bit carry look-ahead adder precisely according to this expression, unless n is small, because maximum fan-in and fan-out restriction is violated at higher
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f
Read more