Search This Blog

Integrated circuit course

Common transistor and diode data

Get link
Facebook
X
Pinterest
Email
Other Apps

By Ahmed Farahat - April 22, 2015

Common transistor and diode data

Common transistor and diode data
Triacs

Common transistor and diode data

Get link
Facebook
X
Pinterest
Email
Other Apps

Comments

Simplification of Logic Expressions:Derivation of Minimal Sums by Karnaugh Map.

By Ahmed Farahat - September 16, 2015

Derivation of Minimal Sums by Karnaugh Map Because of its pictorial nature, a Karnaugh map is a very powerful tool for deriving manually all prime implicants, irredundant disjunctive forms, minimal sums, and also absolute minimal sums. Algebraic concepts such as prime implicants and consensuses can be better understood on a map. One can derive all prime implicants, irredundant disjunctive forms, and minimal sums by the following procedures on Karnaugh maps, when the number of variables is small enough for the map to be manageable. Procedure 28.1: Derivation of Minimal Sums on a Karnaugh Map This procedure consists of three steps: 1. On a Karnaugh map, encircle all the 1-cells with rectangles (also squares as a special case), each of which consists of 2 i 1-cells, choosing i as large as possible, where i is a non-negative integer. Let us call these loops prime implicant loops , since they correspond to prime implicants in the case of the Karnaugh map for four or fewer variable...

Dynamic Random Access Memory:DRAM Memory Cell

By Ahmed Farahat - September 30, 2015

DRAM Memory Cell In early CMOS DRAM storage cell design, three-transistor and four-transistor cells were used in 1-Kb and 4-Kb generations. Later, a particular one-transistor cell, as shown in Figure 55.4(a), became the industry standard [5,6]. The one-transistor (1T) cell achieves smaller cell size and low cost. The cell consists of an n-channel MOSFET and a storage capacitor C s. The charge is stored in the capacitor C s and the n-channel MOSFET functions as the access transistor. The gate of the n-channel MOSFET is connected to the word-line WL and its source/drain is connected to the bit-line. The bit-line has a capacity C BL , including the parasitic load of the connected circuits. The DRAM cell stores one bit of information as the charge on the cell storage capacitor C s. Typical values for the storage capacitor C s are 30 to 50 fF. When the cell stores “1”, the capacitor is charged to V DD – V t. When the stores “0”, the capacitor is discharged to 0 V. During the READ ...

Switched-Capacitor Filters:Performance Limitations

By Ahmed Farahat - October 06, 2015

Performance Limitations The arguments up to now described are valid assuming an ideal behavior of the devices in the SC network (i.e., opamp, switches, and capacitor). However, in the actual realization each of them presents nonidealities which reduce the performance accuracy of the complete SC circuit. The main limitations and their effects are described in the following. Finally, considerations about noise in SC systems conclude this section. Limitation Due to Switches As described before, CMOS switches satisfy both low on-resistance and zero voltage-drop requirements. However they introduce some performance limitations due to their intrinsic CMOS realization. The cross section of a NMOS switch in its on-state is shown in Figure 62.25. The connection between its nodes N1 and N2 is guaranteed by the presence of the channel, made up of the charge Q ch. The amount of charge Q ch can be written as where V i is the channel (input) voltage. Both nodes N1 and N2 are at voltage V ...