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SRAM:Decoder and Word-Line Decoding Circuit [10–13].

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Decoder and Word-Line Decoding Circuit [10–13] Two kinds of decoders are used in SRAM: the row decoder and the column decoder. Row decoders are needed to select one row of word-lines out of a set of rows in the array. A fast decoder can be implemented by using AND/NAND and OR/NOR gates. Figure 52.7 shows the schematic diagrams of static and dynamic AND gate decoders. The static NAND-type structure is chosen due to its low power consumption, that is, only the decoded row transitions. The dynamic structure is chosen due to its speed and power improvement over conventional static NAND gates. From a low-voltage operation standpoint, a dynamic NOR-base decoding would provide lower delay times through the decoder due to the limited amount of stacking of devices. Figure 52.8 shows circuit diagrams of dynamic NOR gates. The dynamic CMOS gate as shown in Figure 52.8(a) consists of input- NMOSs whose drain nodes are precharged to a high level by a PMOS when a clock signal Φ is at a low lev...
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Adders:Carry Look-Ahead Adder.

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Carry Look-Ahead Adder As previously stated, the carry, c i +1, produced at the i -th position is calculated as c i +1 = x i · y i ∨ c i ·( x i ⊕ y i ). This means that a carry is generated if both x i and y i are 1, or an incoming carry is propagated if one of x i and y i is 1 and the other is 0. Therefore, letting g i denote x i y i , we have c i +1 = g i ∨ c i p i , where p i = x i ⊕ y i . Here, g i is the formula for the carry generation condition at the i -th position, i.e., when g i is 1, a carry is generated at this position. Substituting g i –1 ∨ p i –1 c i –1 for c i , we get A carry look-ahead adder can be realized according to this expression, as illustrated in Figure 41.10 for the case of four bits [21]. According to this expression, c i +1’s are calculated at all positions in parallel. It is hard to realize an n -bit carry look-ahead adder precisely according to this expression, unless n is small, because maximum fan-in and fan-out restriction is violated at higher...
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Architecture and Design Flow Optimizations for Power-Aware FPGAs:Low-Power Circuit Techniques.

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Low-Power Circuit Techniques Now let us look at some circuit techniques for reducing power in FPGAs. An obvious approach would be to resize all transistors for optimal power. Since this approach applies equally well to any integrated circuit, we do not discuss this further. Instead, in this section, we describe some of the techniques proposed specifically for FPGAs. One technique to reduce dynamic power consumption in the routing is to use a low-swing interconnect circuit, which uses a lower voltage in the routing fabric. A drawback of most conventional low-swing techniques is the slow speed of the receiver circuit, and the short-circuit current at the receiver end. George et al. [7] mitigated this problem by employing cascode circuitry and differential circuits at the receiver (see Figure 20.6). They assumed pass-transistor switches in the switch blocks, and modified the drivers and receivers for connections with the CLB output and input pins, respectively. This low-swing circuit re...
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