Integrated-circuit amplifiers part1

Integrated-circuit amplifiers

INTRODUCTION

This chapter begins with a brief discussion on the design philosophy of integrated circuits, and how it differs from that of discrete circuits. Next is the comparison of MOS

& BJT in terms of their parameters, characteristics and models. This is followed by current mirror circuits and steering circuits. These circuits are realized using both MOS and BJTs. The chapter ends with general considerations in high frequency response of amplifiers.

IC DESIGN PHOLOSOPHY

Integrated-circuit fabrication technology poses constraints on-and provides opportunities to- the circuit designer. Thus, while chip-area considerations dictate that large-and even moderate-value resistors are to be avoided, constant-current sources are readily available. Large capacitors, for signal coupling and bypass, are not to be used, except perhaps as components external to the IC chip. Even then, the number of such capacitors has to be kept to a minimum; otherwise the number of pin terminals and hence its cost increase. Very small capacitors, in the picofarad and fraction of picofarad range, however, are easy to fabricate in IC MOS technology and can be combined with MOS amplifiers and MOS switches to realize a wide range of signal processing functions, both analog and digital.

As a general rule, in designing IC MOS circuits, one should strive to realize as many of the functions required as possible using MOS transistors only and, when needed, small MOS capacitors. MOS transistor can be sized; that is, their W and L values can be selected, to fit a wide range of requirements. To pack a larger number of devices on the same IC chip, the trend has been to reduce the device dimensions. CMOS process technologies capable of producing devices with a 0.1μm minimum channel length are in use. Such small devices need operate with dc voltage supplies close to 1V. While low- voltage operation can help to reduce power dissipation, it poses lot of challenges to the circuit designer. For example, such MOS transistors must be operated overdrive voltages of only 0.2V or so.

The MOS-amplifier circuits that we shall study will be designed almost entirely using MOSFETs of both polarities-that is, NMOS and PMOS.They are readily available in CMOS process technology. As mentioned earlier, CMOS is currently the most widely used IC technology for both analog and digital as well as combined analog and digital(or mixed-signal)applications. Nevertheless, bipolar integrated circuit still offer many exciting opportunities to the analog design engineer. This is especially the case for general-purpose circuit packages, such as high-quality op amps that are intended for assembly on printed-circuit(pc) board. As well, bipolar circuits can provide much higher output currents and are favoured for certain applications, such as in the automotive industry, for their high reliability under severe environment conditions. Finally, bipolar circuits can be combined with CMOS in innovative and exciting ways.

Introduction to MOSFET Scaling

In 1965, G.E. Moore predicted that the number of transistors in ICs would double after every two years. This prediction has come true and today’s Pentium processor accommodates approximately 14.2million transistors in 1.7 x 2 cm2.The only way to assemble a large number of transistors in given silicon area is to reduce the size of the transistor. The process of reducing vertical and horizontal dimensions of MOSFETs is called scaling. In order to meet Moore’s law, the channel length (L) and width (W) of the MOSFET are reduced by a factor 0.7. If we reduce by a factor of 0.7, the area of the MOSFET, which is W X L, reduces by half. Hence, in the given area we can assemble double the number of transistors.

Scaling is defined as the process of reducing the horizontal and vertical dimensions of a MOS device by some scaling factor S, which is greater than 1. Thus, the scaled device is obtained by simply dividing the key dimensions of the MOSFET such as channel length (L), channel width (W),oxide thickness(tox), and junction depth (Xj),by scaling factor S. MOSFET scaling offers several benefits such as increased component density, increase speed, reduction in power consumption, and cost per chip.

Two type of schemes commonly used for MOSFET scaling are constant –voltage scaling are constant-field scaling.

Constant –Field Scaling: In constant-field scaling, the MOSFET dimensions as well as supply voltages are scaled by the same scaling factor S, greater than 1.The scaling of supply and terminal voltage maintains the same electric field as that of original device; hence such scaling is termed constant-field scaling. Such scaling is also called full scaling, as the geometric dimensions and supply voltages are scaled simultaneously. In order to maintain charge and electric field relationship, the doping densities are scaled by scaling factor S. Constant scaling offers benefits such as increased component density, increased speed, decreased cost, etc. The impact of constant-field scaling on the physical parameters of the MOSFET is summarized in below table. Let MOSFET current before scaling be given by

Hence, the drain current decreases by scaling factor S. Now, before scaling, delay is given by

τ =

Where C is the load capacitance, V is supply voltage, and I is the charging current. we know that in constant –field scaling, C,V and I decrease by a factor of S; hence, the delay after scaling is given by

τ’ = = τ /S …………………(1)

The impact of constant-field scaling on the physical parameters of the MOSFET is summarized in the table below:

Constant-Voltage Scaling: In constant-voltage scaling, the geometrical dimensions of the MOSFET are scaled by the scaling factor S while the supply and terminal voltage are kept constant. In addition to this, the densities are increased by the factor of S2 to maintain the charge electric field relationship. Such scaling is also known as partial scaling because scaling applied only physical dimensions and not to voltages. In this scheme, all voltages are kept constant to maintain the logic level as that of the original device to provide a compatible interface with peripheral circuitry such as I/O devices.

The impact of constant-voltage scaling on the physical parameters of the MOSFET is summarized in the table below:

From Eq.(1) it is clear that in constant-field-scaling, delay decreases by a factor S, while in constant-voltage scaling, delay decreases by the factor S2. Hence, in constant-field scaling improvement in delay is less as compared to constant-voltage scaling. However, power in constant-field scaling is less and power density before and after the scaling remains the same. Thus with the slightest penalty in delay, constant-field scaling offers several advantages compared to constant-voltage scaling. For example, as physical dimensions and voltages are scaled simultaneously by the same factor the electric fields as well as the power density before and after scaling remains the same. Therefore, constant-field scaling improves the reliability of the scaled device, circuits and systems as compared to constant-voltage scaling.

Impact of constant-voltage scaling on electrical properties of MOSFET. Let CGS be the total gate oxide capacitance before scaling given by

Thus the total gate capacitance after scaling decreases by a factor of S. Similarly, we can also show that other parasitic capacitances as well as interconnect capacitances will decrease by scaling factor S. This is a very important result of scaling and applicable to both constant-voltage and constant-field scaling. Let the MOSFET drain current before

scaling be Ids, which is given by

Thus, in constant-voltage scaling, drain current increases by a factor of S. The most important parameter used to compare MOSFET performance is delay, which is given by CV/I , where is C is the load capacitance, V is the supply voltage and I , the charging and discharging current. From eqn(2) and (3) , it is clear that in constant-voltage scaling the total capacitance decreases by factor S, while the current is increased by the same factor S. This decreases the delay of scaled device by S2. In constant voltage scaling, the power dissipation , which is a product of current and voltage, increases by a factor of S. Similarly the power density, which is defined as the power per unit area increases by a factor of S3.In addition to the increased power density, constant-voltage scaling also increases the internal peak electric-fields. The combined effect of increased power density and electric-field eventually leads to device reliability problems, such as oxide break-down and electro-migration. Hence constant field scaling is preferred to constant- voltage scaling.

Short-Channel Effects and Recent Scaling Trends: We have seen that to achieve higher integration density and performance, channel lengths of MOSFETs have been continuously reduced as shown in Table 1. However, in short-channel MOSFETs, such benefits are obtained at the cost of increased short-channel effects, such as the following:

1. Drain induced barrier lowering (DIBL)

2. Punch through effect

3. Threshold voltage roll-off

4. Gate tunneling currents

5. Hot carrier effect

Drain induced barrier lowering (DIBL) A MOSFET is considered a short-channel device when its channel length is of the order of the depletion widths of the source/drain junctions. In a long-channel MOSFET. when gate voltage is sufficiently smaller than threshold voltage, electrons from the source region are prevented from entering into the channel due to the potential barrier of the source-channel junction. However, in short- channel devices, this barrier is lowered by the drain electric field, which eventually allows electron flow into the channel. This flow of electrons gives rise to the drain current, which in turn gives rise to sub-threshold leakage current and static leakage power. In short-channel devices, DIBL effect is controlled by increasing the channel

doping; however, such increased doping will degrade the carrier mobility and, hence, the drain current.

Punch through effect We know that in short-channel devices, channel lengths are of the order of the source/drain depiction region thickness. When drain voltage is increased, the drain depletion region touches the source depletion region. This condition is known as the punch through effect, in which gate voltage loses the control of the channel and the drain current increases sharply. The punch through effect is reduced by using thin gate oxide and high channel doping.

Threshold voltage roll-off For MOSFETs, the threshold voltage expression is derived with the assumption that the depletion bulk charge in the channel region is due to gate voltage. This assumption is valid only for long-channel devices, as the contribution of source/drain depletion charge to channel depletion charge is negligible. However, as channel lengths are reduced, the contribution of source/drain depletion charge increases; hence, the expression for threshold voltage predicts higher threshold voltage than the actual value. Therefore, in short-channel devices, as channel lengths are reduced, the contribution of source/drain depletion charge to total charge in the channel region increases and, hence, the threshold voltage decreases as shown in Fig. 1. The reduction in threshold voltage eventually leads to higher sub-threshold leakage currents, which results in increased static power dissipation.

Gate tunneling currents short-channel MOSFETs require very thin gate oxide to control the various short-channel effects, as mentioned earlier. For example, MOSFETs with a channel length of 65 nm require gate oxide thickness of about 1.2 nm. Such a thin gate oxide consists of only four to five atomic layers and electrons can easily tunnel through the thin oxide. The direct tunneling of electrons across thin gate oxide eventually leads to gate leakage current, which also increases the power dissipation. Hence, tunneling

currents limit the further scaling of oxide thickness. To overcome this problem, the conventional silicon dioxide is replaced with high dielectric constant (high-K) materials such as silicon nitride, hafnium oxide, etc. The high-K material allows higher physical thickness than the conventional silicon dioxide thickness for the same capacitance. Therefore, high-K materials decrease gate tunneling currents and allow further scaling of MOS transistors.

Hot carrier effect The reduction of MOSFET dimensions to achieve higher integration density and performance increases lateral and vertical electric fields in the device. The increased electric field increases the velocity of electrons and holes and, hence, their kinetic energy. Electrons and holes with high kinetic energy are known as hot electrons and hot holes, respectively. Due to high vertical electric field, hot electrons and holes strike or penetrate into the oxide and get trapped at the Si-Si02 interface as well as in the oxide. These trapped carriers modulate the threshold voltage of MOSFETs and degrade the reliability.

COMPARISON OF THE MOSFET AND THE BJT

In this section we present a comparison of the characteristics of the two major electronic devices: the MOSFET and the BJT. To facilitate this comparison, typical values for the important parameters of the two devices are first presented.

Typical Values of MOSFET Parameters

Typical values for the important parameters of NMOS and PMOS transistors fabricated in a number of CMOS processes are shown in Table. Each process is characterized by the minimum allowed channel length, Lmin,thus, for example, in a 0.18-µm process, the smallest transistor has a channel length L = 0.18 µm. The technologies presented in Table are in descending order of channel length, with that having the shortest channel length being the most modern. Although the 0.8-µm process is now obsolete, its data are included to show trends in the values of various parameters. It should also be mentioned that although Table stops at the 0.18-µm process, at the time of this writing (2003), a 0.13-µm fabrication process is commercially available and a 0.09-µm process is in the advanced stages of development. The 0.18-µm process, however, is currently the most popular and the one for which data are widely available. The trends shown help us to illustrate design trade-offs as well as enable us to work out design examples and problems with parameter values that are as realistic as possible.

TABLE 3 : Typical Values of CMOS Device Parameters

As indicated in Table-3, the trend has been to reduce the minimum allowable channel length. This trend has been motivated by the desire to pack more transistors on a chip as well as to operate at higher speeds or, in analog terms, over wider bandwidths.

Observe that the oxide thickness, tox, scales down with the channel length, reaching 4 nm for the 0.18-µm process. Since the oxide capacitance Cox is inversely proportional to tox, we see that Cox increases as the technology scales down. The surface mobility µ decreases as the technology minimum-feature size is decreased, and µp decreases much faster than µn. As a result, the ratio of µp to µn has been decreasing with each generation of technology, falling from about 0.5 for older technologies to 0.2 or so for the newer ones. Despite the reduction of ) µn and µp, the transconductance parameters k'n = µn Cox and k'p = µn Cox have been steadily increasing. As a result, modern short-channel devices achieve required levels of bias currents at lower overdrive voltages. As well, they achieve higher transconductanc, a major advantage.

Although the magnitudes of the threshold voltages Vtn and Vtp have been decreasing with Lmia from about 0.7-0.8 V to 0.4-0.5 V, the reduction has not been as large as that of the power supply VDD. The latter has been reduced dramatically, from 5 V for older technologies to 1.8 V for the 0.18-µm process. This reduction has been necessitated by die need to keep the electric fields in the smaller devices from reaching very high values. Another reason for reducing VDD is to keep power dissipation as low as possible given that the IC chip now has a much larger number of transistors.1

The fact that in modern short-channel CMOS processes |Vt| has become a much larger proportion of the power-supply voltage poses a serious challenge to the circuit design engineer. Recalling that | VGS| = | Vt| +|Vov|, where Vov is the overdrive voltage, to keep

| VGS| reasonably small, |Vov| for modern technologies is usually in the range of 0.2 V to

0.3 V. To appreciate this point further, recall that to operate a MOSFET in the saturation region. |VDS| must exceed | Vov|; thus, to be able to have a number of devices stacked between the power-supply rails in a regime in which VDD is only 1.8 V or lower, we need to keep |V0V| as low as possible. We will shortly see, however, that operating at a low | Vov| has some drawbacks.

Another significant though undesirable feature of modern submicron CMOS technologies is that the channel length modulation effect is very pronounced. As a result of V'A steadily decreasing, which combined with the decreasing values of L has caused the Early voltage V A = V'A L to become very small. Correspondingly, short-channel MOSFETs exhibit low output resistances.

We know that two major MOSFET capacitances are Cgs and Cgd. While Cgs has an overlap component, Cgd is entirely an overlap capacitance. Both Cgd and the overlap component of Cgs are almost equal and are denoted Cov. The last line of Table provides the value Cov per micron of gate width. Although the normalized Cov has been staying more or less constant with the reduction in Lmin, we will shortly see that the shorter devices exhibit much higher operating speeds and wider amplifier bandwidths than the longer devices. Specifically, we will, for example, see that fT for a 0.25-µm NMOS transistor can be as high as 10 GHz.

Typical Values of IC BJT Parameters

Table below provides typical values of major parameters that characterize integrated- circuit bipolar transistors. Data are provided for devices fabricated in two different processes: the standard, old process, known as the "high-voltage process"; and an advanced process, referred to as a "low-voltage process." For each process we show the parameters of the standard npn transistor and those of a special type of pnp transistor known as a lateral (as opposed to vertical as in the npn case) pnp. In this regard we should mention that a major drawback of standard bipolar integrated-circuit fabrication processes has been the lack of pnp transistors of a quality equal to that of the npn devices. Rather, there are a number of pnp implementations for which the lateral pnp is the most economical to fabricate. Unfortunately, however, as should be evident from Table the

TABLE -4 : Typical Parameter Values for BJTs1

lateral pnp has characteristics that are much inferior to those of the npn. Note in particular the lower value of β and the much larger value of the forward transit time τF that determines the emitter-base diffusion capacitance Cde and, hence, the transistor speed of operation. The data in Table can be used to show that the unity-gain frequency of the lateral pnp is two orders of magnitude lower than that of the npn transistor fabricated in the same process. Another important difference between the lateral pnp and the corresponding npn transistor is the value of collector current at which their β values reach their maximums: For the high-voltage process, for example, this current is in the tens of microamperes range for the pnp and in the milliampere range for the npn. On the positive side, the problem of the lack of high-quality pnp transistors has spurred analog circuit designers to come up with highly innovative circuit topologies that either minimize the use of pnp transistors or minimize the dependence of circuit performance on that of the pnp.

The dramatic reduction in device size achieved in the advanced low-voltage process should be evident from Table. As a result, the scale current Is also has been reduced by about three orders of magnitude. Here we should note that the base width, WB, achieved in the advanced process is of the order of 0.1 µm, as compared to a few microns in the standard high-voltage process. Note also the dramatic increase in speed; for the low- voltage npn transistor, τF = 10 ps as opposed to 0.35 ns in the high-voltage process. As a result, fT for the modem npn transistor is 10 GHz to 25 GHz, as compared to the 400 MHz to 600 MHz achieved in the high-voltage process. Although the Early voltage, VA, for the modern process is lower than its value in the old high-voltage process, it is still reasonably high at 35 V. Another feature of the advanced process—and one that is not obvious from Table—is that β for the npn peaks at a collector current of 50 µA or so. Finally, note that as the name implies, npn transistors fabricated in the low-voltage process break down at collector-emitter voltages of 8 V, as compared to 50 V or so for the high-voltage process. Thus, while circuits designed with standard high-voltage process utilize power supplies of ± 15 V (e.g., in commercially available op amps of the 741 type), the total power-supply voltage utilized with modern bipolar devices is 5 V (or even 3.3 V to achieve compatibility with some of the submicron CMOS processes).

Comparison of Important Characteristics

Table -5 provides a compilation of the important characteristics of the NMOS and the npn transistors. The material is presented in a manner that facilitates comparison. It is to be noted that the PMOS and the pnp transistors can be compared in a similar way.

Operating Conditions At the outset, we shall use active mode or active region to denote both the active mode of operation of the BJT and the saturation-mode of operation of the MOSFET.

The conditions for operating in the active mode are very similar for the two devices: The explicit threshold Vt of the MOSFET has VBEon as its implicit counterpart in the BJT. Furthermore, for modern processes, VBEon and Vt are almost equal.

Also, pinching off the channel of the MOSFET at the drain end is very similar to reverse biasing the CBJ of the BJT. Note, however, that the asymmetry of the BJT results in VBCon and VBEon being unequal, while in the symmetrical MOSFET the operative threshold voltages at the source and the drain ends of the channel are identical (Vt). Finally, for both the MOSFET and the BJT to operate in the active mode, the voltage across the device (vDS, vCE) must be at least 0.2 V to 0.3 V.

Current-Voltage Characteristics The square-law control characteristic, iD-vGS, in the MOSFET should be contrasted with the exponential control characteristic, ic,—vBE, of the BJT. Obviously, the latter is a much more sensitive relationship, with the result that ic can vary over a very wide range (five decades or more) within the same BJT. In the MOSFET, the range of iD achieved in the same device is much more limited. To appreciate this point further, consider the parabolic relationship between iD and vov, and recall from our discussion above that vov is usually kept in a narrow range (0.2 V to 0.4 V).

Next we consider the effect of the device dimensions on its current. For the bipolar transistor the control parameter is the area of the emitter-base junction (EBJ), AE which determines the scale current Is. It can be varied over a relatively narrow range, such as 10 to 1. Thus, while the emitter area can be used to achieve current scaling in an IC (as we shall see in the next section in connection with the design of current mirrors) its narrow range of variation reduces its significance as a design parameter. This is particularly so if we compare AE with its counterpart in the MOSFET, the aspect ratio W/L. MOSFET devices can be designed with W/L ratios in a wide range, such as 0.1 to 100. As a result W/L is a very significant MOS design parameter. Like AE, it is also used in current scaling, as we shall see in the next section. Combining the possible range of variation of vov and W/L, one can design MOS transistors to operate over an iD range of four decades or so.

The channel-length modulation in the MOSFET and the base-width modulation in the BJT are similarly modeled and give rise to the dependence of iD(ic) on vDS(vCE) and, hence, to the finite output resistance r0 in the active region. Two important differences, however, exist. In the BJT, VA is solely a process-technology parameter and does not depend on the dimensions of the BJT. In the MOSFET, the situation is quite different: VA = V'AL, where VA' is a process-technology parameter and L is the channel length used. Also, in modern submicron processes, V'A is very low, resulting in VA values much lower than the corresponding values for the BJT.

The last, and perhaps most important, difference between the current-voltage characteristics of the two devices concerns the input current into the control terminal: While the gate current of the MOSFET is practically zero and the input resistance looking into the gate is practically infinite, the BJT draws base current iB that is proportional to the collector current; that is, iB = ic/β. The finite base current and the corresponding finite input resistance looking into the base is a definite disadvantage of the BJT in comparison to the MOSFET. Indeed, it is the infinite input resistance of the MOSFET that has made possible analog and digital circuit applications that are not feasible with the BJT. Examples include dynamic digital memory and switched-capacitor filters.

EXAMPLE

(a) For an NMOS transistor with W/L = 10 fabricated in the 0.18-µm process, find the values of Vov and VGS required to operate the device at ID = 100 µA. Ignore channel- length modulation.

(b) Find VBE for an npn transistor fabricated in the low-voltage process and operated at Ic

= 100 µA. Ignore base-width modulation.

Solution

Low-Frequency Small-Signal Models The low-frequency models for the two devices are very similar except, of course, for the finite base current (finite β) of the BJT, which gives rise to rπ in the hybrid –π model and to the unequal currents in the emitter and collector in the T models (a < 1). Here it is interesting to note that the low-frequency small-signal models become identical if one thinks of the MOSFET as a BJT with β = ∞ (α = 1).

For both devices, the hybrid-π model indicates that the open-circuit voltage gain obtained from gate to drain (base to collector) with the source (emitter) grounded is -gmr0. It follows that gmr0 is the maximum gain available from a single transistor of either type. This important transistor parameter is given the name intrinsic gain and is denoted A0.

Although not included in the MOSFET low-frequency model shown in Table, the body effect can have a significant implication for the operation of the MOSFET as an amplifier. In simple terms, if the body (substrate) is not connected to the source, it can act as a second gate for the MOSFET. The voltage signal that develops between the body and the source, vbs, gives rise to a drain current component gmb = vbs, where the body transconductance gmb is proportional to gm; that is, gmb = χgm, where the factor χ is in the range of 0.1 to 0.2. We shall take the body effect into account in the study of IC MOS amplifiers in the succeeding sections. The body effect has no counterpart in the BJT.

The Transconductance For the BJT, the transconductance gm depends only on the dc collector current Ic. (Recall that VT is a physical constant =0.025 V at room temperature). It is interesting to observe that gm does not depend on the geometry of the BJT, and its

dependence on the EBJ area is only through the effect of the area on the total collector current Ic- Similarly, the dependence of gm on VBE is only through the fact that VBE determines the total current in the collector. By contrast, gm of the MOSFET depends on ID, Vov, and W/L. Therefore, we use three different (but equivalent) formulas to express gm of the MOSFET.

The first formula given in Table for the MOSFET's gm is the most directly comparable with the formula for the BJT. It indicates that for the same operating current, gm of the MOSFET is much smaller than that of the BJT. This is because Vov/2 is in the range of

1.1 V to 0.2 V, which is four to eight times the corresponding term in the BJT's formula, namely VT.

The second formula for the MOSFET's gm indicates that for a given device (i.e., given W/L), gm is proportional to Vov. Thus a higher gm is obtained by operating the MOSFET at a higher overdrive voltage. However, we should recall the limitations imposed on the magnitude of Vov by the limited value of VDD. Put differently, the need to obtain a reasonably high gm constrains the designer's interest in reducing Vov.

The third gm formula shows that for a given transistor (i.e., given W/L), gm is proportional to . This should be contrasted with the bipolar case, where gm is directly proportional to IC.

Output Resistance The output resistance for both devices is determined by similar formulas, with ro being the ratio of VA to the bias current (ID or Ic). Thus, for both transistors, ro is inversely proportional to the bias current. The difference in nature and magnitude of VA between the two devices has already been discussed.

Intrinsic Gain The intrinsic gain A0 of the BJT is the ratio of VA which is solely a process parameter (35 V to 130 V), and VT, which is a physical parameter (0.025 V at room temperature). Thus A0 of a BJT is independent of the device junction area and of the operating current, and its value ranges from 1000 V/V to 5000 V/V. The situation in the MOSFET ' is very different: Table provides three different (but equivalent) formulas for expressing the MOSFET's intrinsic gain. The first formula is the one most directly comparable to that of the BJT. Here, however, we note the following:

1. The quantity in the denominator is Vov/2. which is a design parameter, and although it is becoming smaller in designs using short-channel technologies, it is still much larger than VT.

2. The numerator quantity VA is both process- and device-dependent, and its value has been steadily decreasing.

As a result, the intrinsic gain realized in a single MOSFET amplifier stage fabricated in a modern short-channel technology is only 20 V/V to 40 V/V, almost two orders of magnitude lower than that for a BJT.

The third formula given for A0 in Table points out a very interesting fact: For a given process technology (V’A and µn Cax) and a given device (W/L), the intrinsic gain is inversely proportional to . This is illustrated in Fig below which shows a typical plot of A0 versus the bias current ID. It is clear that the gain increases as the bias current is lowered. The gain, however, levels off at very low currents. This is because the MOSFET enters the sub threshold region of operation, where it becomes very much like a BJT with an exponential current-voltage characteristic. The intrinsic gain then becomes constant, just as in BJT. Although a higher gain is achieved at lower bias currents, the price paid is a lower gm and less ability to drive capacitive loads and thus a decrease in bandwidth.

EXAMPLE

It is required to compare the values of gm, input resistance at the gate (base). r0, and A0 for an NMOS transistor fabricated in the 0.25-µm technology specified in Table and an npn transistor fabricated in the low-voltage technology specified in Table. Assume both devices are operating at a drain (collector) current of 100 µA. For the MOSFET, let L =

0.4 µm and W = 4 µm, and specify the required Vov.

Solution

For the NMOS transistor,

High-Frequency Operation The simplified high-frequency equivalent circuits for the MOSFET and the BJT are very similar, and so are the formulas for determining their unity-gain frequency (also called transition frequency) fT. Recall that fT is a measure of the intrinsic bandwidth of the transistor itself and does not take into account the effects of capacitive loads. We shall address the issue of capacitive loads shortly. For the time being, note the striking similarity between the approximate formulas given in Table 6.6 for the value of fT of the two devices. In both cases fT is inversely proportional to the square of the critical dimension of the device: the channel length for the MOSFET and the base width for the BJT. These formulas also clearly indicate that shorter-channel MOSFETs" and narrower-base BJTs are inherently capable of a wider bandwidth of operation. It is also important to note that while for the BJT the approximate expression for fT indicates that it is entirely process determined, the corresponding expression for the MOSFET shows that fT is proportional to the overdrive voltage Vov. Thus we have conflicting requirements on Vov: While a higher low-frequency gain is achieved by operating at a low Vov, wider bandwidth requires an increase in Vov. Therefore the selection of a value for Vov involves, among \ other considerations, a trade-off between gain and bandwidth.

For npn transistors fabricated in the modern low-voltage process, fT is in the range of 10 GHz to 20 GHz as compared to the 400 MHz to 600 MHz obtained with the standard

high-voltage process. In the MOS case, NMOS transistors fabricated in a modern submicron technology, such as the 0.18-µm process, achieve fT values in the range of 5 GHz to 15 GHz.

Before leaving the subject of high-frequency operation, let's look into the effect of a capacitive load on the bandwidth of the common-source (common-emitter) amplifier. For this purpose we shall assume that the frequencies of interest are much lower than fT of the transistor. Hence we shall not take the transistor capacitances into account. Figure shows a common-source amplifier with a capacitive load CL. The voltage gain from gate to drain can be found as follows:

Thus the gain has, as expected, a low-frequency value of gmr0 = A0 and a frequency response of the single-time-constant (STC) low-pass type with a break (pole) frequency at

Obviously this pole is formed by ro and CL. A sketch of the magnitude of gain versus frequency is shown in Fig. We observe that the gain crosses the 0-dB line at frequency wt,

FIGURE3 Frequency response of a CS amplifier loaded with a capacitance CL and fed with an ideal voltage source. It is assumed that the transistor is operating at frequencies much lower than fT, and thus the internal capacitances are not taken into account.

Thus

Wt =

That is, the unity-gain frequency or, equivalently, the gain-bandwidth product wt, is the ratio gm and CL. We thus clearly see that for a given capacitive load CL, a larger gain-bandwidth product is achieved by operating the MOSFET at a higher gm. Identical analysis and conclusions apply to the case of the BJT. In each case, bandwidth increases as bias current is increased.

Design Parameters For the BJT there are three design parameters—Ic, VBE, and Is (or, equivalently, the area of the emitter-base junction)—of which any two can be selected by designer. However, since Ic is exponentially related to VBE and is very sensitive to the value of VBE (VBE changes by only 60 mV for a factor of 10 change in Ic), Ic is much more than VBE as a design parameter. As mentioned earlier, the utility of the EBJ area as a

Figure4 Increasing I or W/L increases the bandwidth of a MOSFET amplifier loaded by a constant capacitanc D

design parameter is rather limited because of the narrow range over which AE can vary. It follows that for the BJT there is only one effective design parameter: the collector current 1c. Finally, note that we have not considered VCE to be a design parameter, since its effect on Ic is only secondary. Of course, VCE affects the output signal swing.

For the MOSFET there are four design parameters—ID, Vov, L, and W—of which any three can be selected by the designer. For analog circuit applications the trade-off in selecting a value for L is between the higher speeds of operation (wider amplifier bandwidth) obtained at lower values of L and the higher intrinsic gain obtained at larger values of L. Usually one selects an L of about 25% to 50% greater than Lmin.

The second design parameter is Vov. We have already made numerous remarks about , the effect of the value of Vov on performance. Usually, for submicron technologies, Vov is selected in the range of 0.2 V to 0.4 V.

Once values for L and Vov are selected, the designer is left with the selection of the value of ID or W (or, equivalently, W/L). For a given process and for the selected values of L and Vov, lD is proportional to W/L. It is important to note that the choice of ID or, equivalently, of W/L has no bearing on the value of intrinsic gain A0 and the transition frequency fT. However, it affects the value of gm and hence the gain-bandwidth product. Figure illustrates this point by showing how the gain of a common-source amplifier operated at a constant Vov varies with ID (or, equivalently, W/L). Note that while the dc gain remains unchanged, increasing W/L and, correspondingly, ID increases the bandwidth, proportionally. This, however, assumes that the load capacitance CL is not affected by the device size, an assumption that may not be entirely justified in some cases.

Combining MOS and Bipolar Transistors-BiCMOS Circuits

It is evident that the BJT has the advantage over the MOSFET of a much higher transconductance (gm) at the same value of dc bias current. Thus, in addition to realizing much higher voltage gains per amplifier stage, bipolar transistor amplifiers have superior high-frequency performance compared to their MOS counterparts.

On the other hand, the practically infinite input resistance at the gate of a MOSFET makes it possible to design amplifiers with extremely high input resistances and an almost zero input bias current. Also, the MOSFET provides an excellent implementation of a switch, a fact that has made CMOS technology capable of realizing a host of analog circuit functions that are not possible with bipolar transistors.

It can thus be seen that each of the two transistor types has its own distinct and unique advantages: Bipolar technology has been extremely useful in the design of very-high- quality general-purpose circuit building blocks, such as op amps. On the other hand, CMOS, with its very high packing density and its suitability for both digital and analog circuits, has become the technology of choice for the implementation of very-large-scale integrated circuits. Nevertheless, the performance of CMOS circuits can be improved if the designer has available (on the same chip) bipolar transistors that can be employed in functions that require their high gm and excellent current-driving capability. A technology that allows the fabrication of high-quality bipolar transistors on the same chip as CMOS circuits called BiCMOS.

Validity of the Square-Law MOSFET Model

We conclude this section with a comment on the validity of the simple square-law model we have been using to describe the operation of the MOS transistor. While this simple model works well for devices with relatively long channels (>1 µm) it does not provide an accurate representation of the operation of short-channel devices. This is because a number of physical phenomena come into play in these submicron devices, resulting in what are called short-channel effects. Although the study of short-channel effects is beyond the scope, it should be mentioned that MOSFET models have been developed that take these effects into account. However, they are understandably quite complex and do not lend themselves to hand analysis of the type needed to develop insight into circuit operation. Rather, these models are suitable for computer simulation and are indeed used in SPICE. For quick, manual analysis, however, we will continue to use the square-law

model which is the basis for the comparison in Table above.

IC BIASING-CURRENT SOURCES, CURRENT MIRRORS & CURRENT- STEERING CIRCUITS

Biasing in integrated-circuit design is based on the use of constant-current sources. On an IC chip with a number of amplifier stages, a constant dc current (called a reference current) is generated at one location and is then replicated at various other locations for biasing the various amplifier stages through a process known as current steering. This approach has the advantage that the effort expended on generating a predictable and stable reference current, usually utilizing a precision resistor external to the chip, need not be repeated for every amplifier stage. Furthermore, the bias currents of the various stages track each other in case of changes in power-supply voltage or in temperature.

In this section we study circuit building blocks and techniques employed in the bias design of IC amplifiers. These circuits are also utilized as amplifier load elements.