Integrated-circuit amplifiers (contd.) part3
THE SOURCE AND EMITTER FOLLOWERS
In the following discussion we consider their IC versions of source and emitter followers, with a special emphasis on their high-frequency response.
The Source Follower
Figure 34(a) shows an IC source follower biased by a constant-current source I, which is usually implemented using an NMOS current mirror. The source follower would generally be part of a larger circuit that determines the dc voltage at the transistor gate. Here, vi is the input signal appearing at the gate and RL represents the combination of a load resistance and the output resistance and the current-source I.
The low-frequency small-signal model of the source follower is shown in Fig- 34(b)- Observe that ro appears in parallel with RL and thus can be combined with it. Also, the controlled current-source gmbvbs feeds its current into the source terminal, where the voltage is -vbs. Thus we can use the source-absorption theorem to replace the current source with a resistance 1 /gmb between the source and ground, this can then be combined with RL and r0 . With these two simplifications, the equivalent circuit takes the form shown in Fig. 34(c), where
which, as expected, is less than unity. To obtain the open-circuit voltage gain, we set RL in Eq. (133) to ∞, which reduces R'L to ro II (1 /gmb). Substituting this value for R'L in Eq.
(135) gives
Thus the highest value possible for the voltage gain of the source follower is limited to l/ (l χ), which is typically 0.8 V/V to 0.9 V/V.
Finally, we can find the output resistance Ro of the source follower either using the equivalent circuit of Fig. 34(c) or by inspection of the circuit in Fig. 34 (d) as
Similar to the discrete source follower, the IC source follower can be used as the output stage of a multistage amplifier to provide a low output resistance for driving low- impedance loads. It is also used to shift the dc level of the signal by an amount equal to VGS.
Frequency Response of the Source Follower
A major advantage of the source follower is its excellent high-frequency response. This comes about because, as we shall now see, none of the internal capacitances suffers from the Miller effect. Figure 35(a) shows the high-frequency equivalent circuit of a source follower fed with a signal Vsjg from a source having a resistance Rsig. In addition to the MOSFET capacitances Cgs and Cgd, a capacitance CL is included between the output node and ground to account for the source-to-body capacitance Csb as well as any actual load capacitance.
The simplifications performed above on the low-frequency equivalent circuit can be applied to the high-frequency model of Fig. 35(a) to obtain the equivalent circuit in Fig. 35(b), where R’L is given by Eq. (133). Although one can derive an expression for the transfer function of this circuit, the resulting expression will be too complicated to yield insight regarding the role that each of the three capacitances plays. Rather, we shall first determine the location of the transmission zeros and then use the method of open-circuit time constants to estimate the 3-dB frequency, f3dB.
Although there are three capacitances in the circuit of Fig. 35(b), the transfer function is of the second order. This is because the three capacitances form a continuous loop. To determine the location of the two transmission zeros, refer to the circuit in Fig. 35(b), and note that v0 is zero at the frequency at which CL has a zero impedance and thus acts as a short circuit across the output, which is ω or s = ∞. Also, vo will be zero at the value of s that causes the current into the impedance R’L II CL to be zero. Since this current is (gm + sCgs)vgs -the transmission zero will be at s = sz, where
Next, we turn our attention to the poles. Specifically, we will find the resistance seen by each of three capacitances Cgd, Cgs, and CL and then compute the time constant associated with each. With Vsig set to zero and Cgs and CL assumed to be open circuited, we find by inspection that the resistance Rgd seen by Cgd is given by
Next, we consider the effect of Cgs The resistance Rgs seen by Cgs can be determined by straightforward analysis of the circuit in Fig. 35(c) to obtain
We note that the factor (1 + gmR’L) in the denominator will result in reducing the effective resistance with which Cgs interacts. In the absence of the two other capacitances, Cgs together with Rgs introduce a pole with frequency l/2πCgsRgs.
Finally, it is easy to see from the circuit in Fig. 35(b) that CL interacts with RL // Ro that is.
Usually, R0 (Eq. 138) is low. Thus RCL will be low. and the effect of CL will be small. Nevertheless, all three time constants can be added to obtain τH and hence fH,
The Emitter Follower
Figure 36(a) shows an emitter follower suitable for IC fabrication. It is biased by a constant-current source, I. However, the circuit that sets the DC voltage at the base is not shown. The emitter follower is fed with a signal Vsig from a source with resistance Rsig. The resistance RL shown at the output, includes the output resistance of current source I as well as any actual load resistance.
Analysis of the emitter follower of Fig. 36(a) will give low-frequency gain,
Here ro’ is parallel combination of output resistances of current source transistor and amplifying transistor.
The circuit can be used as voltage buffer because of unity gain, high input resistance and low output resistance.
Figure 36(b) shows the high-frequency equivalent circuit. Lumping ro together with RL and rx together with Rsig and making a slight change in the way the circuit is drawn results in the simplified equivalent circuit shown in Fig. 36(c). We will follow a procedure for the analysis of this circuit similar to that used above for the source follower. Specifically, to obtain the location of the transmission zero, note that Vo will be zero at the frequency sz for which the current fed to R'L is zero:
which is on the negative real-axis of the s-plane and has a frequency
This frequency is very close to the unity –gain frequency ωT of the transistor. The other transmission zero is at s =∞. This is because at this frequency, Cµ acts as a short circuit, making Vπ zero, and hence Vo will be zero.
Next, we determine the resistances seen by Cµ and Cπ. For Cµ , the resistance it sees, Rµ, is the parallel equivalent of R’sig and the input resistance looking into B’; that is,
Equation (155) indicates that Rµ will be smaller than R’sig and since cµ is usually very small, the time constant CµRµ will be correspondingly small.
The resistance Rπ seen by Cπ can be determined using an analysis similar to that employed for the determination of Rgs in the MOSFET case. The result is
We observe that the term R’L/re will usually make the denominator much greater than unity thus rendering Rπ rather low. Thus, the time constant CπRπ will be small. The end result is that the 3-dB frequency fH of the emitter follower will usually be very high.
(6.184)
SOME USEFUL TRANSISTOR PAIRINGS
The cascode configuration studied above combines CS and CG MOS transistors (CE and CB bipolar transistors) to great advantage. The key to the superior performance is that the transistor pairing is done in a way that maximizes the advantages and minimizes the shortcomings of each of the two individual configurations. In this section we study a number of other such transistor pairings. In each case the transistor pair can be thought of as a compound device; thus the resulting amplifier may be considered as a single stage.
The CD-CS, CC-CE and CD-CE Configurations
Figure 37(a) shows an amplifier formed by cascading a common-drain (source-follower) transistor Q1 with a common-source transistor Q2. As should be expected, the voltage of the circuit will be a little lower than that of the CS amplifier. The advantage of this circuit
configuration, however, lies in its bandwidth, which is much wider than that obtained in a CS amplifier. To see how this comes about, note that the CS transistor Q2 will still exhibit a Miller’s effect that results in a large input capacitance, Cin2, between its gate and ground. However, the resistance that this capacitance interacts with will be much lower than Rsig the buffering action of the source follower causes a relatively low resistance, approximately equal to a l/(gm1 + gmb1), to appear between the source of Q1 and ground across Cin2.
The bipolar counterpart of the CD-CS circuit is shown in Fig. 37(b). Besides achieving a wider bandwidth than that obtained with a CE amplifier, the CC-CE configuration has an important additional advantage: The input resistance is increased by a factor equal to (β1 + 1). Finally, we show in Fig. 37(c) the BiCMOS version of this circuit type. Observe that Q1 provides the amplifier with an infinite input resistance. Also, note that Q2 provides the amplifier with a high gm as compared to that obtained in the MOSFET circuit in Fig. 37(a) and hence high gain.
EXAMPLE
Consider a CC-CE amplifier such as that in Fig. 37(b) with the following specifications: I1 = I2 = 1mA and identical transistors with β = 100, fT = 400 MHz, and Cµ = 2 pF. Let the amplifier be fed with a source Vsig having a resistance Rsig = 4 kW, and assume a load resistance of 4 kW. Find voltage gain AM , and estimate the 3-dB frequency, fH. Compare the results with those obtained with a CE amplifier operating under the same conditions. For simplicity, neglect ro and rx.
Solution
To determine fH we use the method of open-circuit time constants. Figure 38(b) shows the circuit with Vsig set to zero and the four capacitances indicated. Capacitance Cµ1 sees a resistance R µ1
Capacitance Cµ2 sees a resistance Rµ2 To determine R µ2 we refer to the analysis of the frequency response of the CE amplifier Section to obtain
We now can determine τH from
We observe that C π1 and C π2 play a very minor role in determining the high-frequency response. As expected, Cµ2, through the Miller effect plays the most significant role. Also, Cµ1 which interacts directly with (Rsig II Rin), also plays an important role. The 3-dB frequency fH can be found as follows:
For comparison, we evaluate AM and fH of a CE amplifier operating under the same conditions. Refer to Fig. 38(c). The voltage gain AM is given by
Figure 39(a) shows a popular BJT circuit known as the Darlington configuration. It can be thought of as a variation of the CC-CE circuit with the collector of Q1 connected to that of Q2. Alternatively, the Darlington pair can be thought of as a composite transistor with β = β1β2 . It can therefore be used to implement a high-performance voltage follower, as illustrated in Fig. 39(b). Note that in this application the circuit can be considered as the cascade connection of two common-collector transistors (i.e., a CC-CC configuration).
Since the transistor β depends on the dc bias current, it is possible that Q1 will be operating at a very low β, rendering the β-multiplication effect of the Darlington pair rather ineffective. A simple solution to this problem is to provide a bias current for Q1 as shown in Fig. (39c).
The CC-CB and CD-CG Configurations
Cascading an emitter follower with a common-base amplifier, as shown in Fig. 40(a) results in a circuit with a low-frequency gain approximately equal to that of the CB but with the problem of the low input resistance of the CB solved by the buffering action of the CC stage. Since neither the CC nor the CB amplifier suffers from the Miller effect, the CC-CB
configuration has excellent high-frequency performance. Note that the biasing current sources shown in Fig. 40(a) ensure that each of Q1 and Q2 is operating at a bias current
I. We are not showing, however, how the dc voltage at the base of Q1 is set or the circuit
that determines the dc voltage at the collector of Q2. Both issues are usually looked after in the larger circuit of which the CC-CB amplifier is part.
An interesting version of the CC-CB configuration is shown in Fig. 40(b). Here the CB stage is implemented with a pnp transistor. Although only one current source is now
needed, observe that we also need to establish an appropriate voltage at the base of Q2.
This circuit is part of the internal circuit of the popular 741 op amp.
The MOSFET version of the circuit in Fig. 40(a) is the CD-CG amplifier shown in Fig. 40(c).
We now briefly analyze the circuit in Fig. 40(a) to determine its gain AM and its high- frequency response. The analysis applies directly to the circuit in Fig. 40(b) and, with appropriate change of component and parameter names, to the MOSFET version in Fig. 40(c). For simplicity we shall neglect rx and ro of both transistors. The input resistance Rin is given by
The high-frequency analysis is illustrated in Fig. 41(a). Here we have drawn the hybrid- π equivalent circuit for each of Q1 and Q2. Recalling that the two transistors are operating at equal bias currents, their corresponding model components will be equal (i.e. rπ1 = r π2, cπ1 = cπ2 etc). With this in mind the reader should be able to see that V π1 = -V π2 and the horizontal line through the node labeled E in Fig. 41(a) can be deleted. Thus the circuit reduces to that in Fig. 41(b). This is a very attractive outcome because the circuit shows clearly the two poles that determine the high-frequency response: The pole at the input, with a frequency fp1 is
and the pole at the output, with a frequency fP2, is
This result is also intuitively obvious: The input impedance at B1 of the circuit in Fig. 41 consists of the series connection of rπ1 and r π2 in parallel with the series connection of C π1 and C π2. Then there is Cµ in parallel. At the output, we simply have RL in parallel with
Cµ
Whether one of the two poles is dominant will depend on the relative values of Rsig and
RL. If the two poles are close to each other, then the 3-dB frequency fH can be 81
determined either by exact analysis—that is, finding the frequency at which the gain is down by 3 dB— or by using the approximate formula derived in unit2(last section),
CURRENT-MIRROR CIRCUITS WITH IMPROVED PERFORMANCE
Current sources play an important role in the design of IC amplifiers: The constant- current source is used both in biasing and as active load. Simple forms of both MOS and bipolar current sources and, more generally, current mirrors are already studied.
However, two performance parameters need to be addressed: the accuracy of the current transfer ratio of the mirror and the output resistance of the current source.
We may recall that the accuracy of the current transfer ratio suffers particularly from the finite β of the BJT. The output resistance, which in the simple circuits is limited to r0 of the MOSFET and the BJT, also reduces accuracy and, much more seriously, severely limits the gain available from cascode amplifiers. In this section we study MOS and bipolar current mirrors with more accurate current transfer ratios and higher output resistances.
Cascode MOS Mirrors
Figure 42 shows the basic cascode current mirror. Observe that in addition to the diode- connected transistor Q1, which forms the basic mirror Q1-Q2, another diode-connected transistor, Q4, is used to provide a suitable bias voltage for the gate of the cascode transistor Q3 To determine the output resistance of the cascode mirror at the drain of Q3, we set IREF to zero. Also, since Q1 and Q4 have a relatively small incremental resistance, each of approximately 1/gm, the incremental voltages across them will be small, and we can assume that the gates of Q3 and Q2 are both grounded. Thus the output resistance Ro will be that of the CG transistor Q3, which has a resistance rol in its source. Equation (86) can be adapted to obtain
Thus, as expected, cascoding raises the output resistance of the current source by the factor gm3ro3 which is the intrinsic gain of the cascode transistor.
A drawback of the cascode current mirror is that it consumes a relatively large portion of e steadily shrinking supply voltage VDD. While the simple MOS mirror operates properly with a voltage as low as Vov across its output transistor, the cascode circuit of Fig. 42 requires a minimum voltage of Vt+ 2Vov. This is because the gate of Q3 is at 2VGS = 2 Vt + 2Vov. Thus the minimum voltage required across the output of the cascode mirror is 1 V or so. This obviously limits the signal swing at the output of the mirror (i.e.. at the output of the amplifier that utilizes this current source as a load).
A Bipolar Mirror with Base-Current Compensation
Figure 43 shows a bipolar current mirror with a current transfer ratio that is much less dependent on β than that of the simple current mirror. The reduced dependence on β is obtained by including transistor Q3, the emitter of which supplies the base currents of Q1 and Q2. The sum of the base currents is then divided by (β3 + 1), resulting in a much smaller error current that has to be supplied by IREF. Detailed analysis is shown on the circuit diagram; it is based on the assumption mat Q1 and Q2 are matched and thus have equal collector currents, Ic. A node equation at the node labeled x gives
which means that the error due to finite β has been reduced from 2/β in the simple mirror to 2/β2, a tremendous improvement. Unfortunately, however, the output resistance remains approximately equal to that of the simple mirror, namely r0 . If a reference current IREF is not available, we simply connect node x to the power supply Vcc through a resistance R. The result is a reference current given by
The Wilson Current Mirror
, (1 + 2/W
A simple but clever modification of the basic bipolar mirror results in both reducing the β dependence and increasing the output resistance. The circuit, known as the Wilson mirror after its inventor, George Wilson, an IC design engineer working for Tektronix, is shown in Fig. 44(a). The analysis to determine the effect of finite β on the current transfer
This analysis assumes that Q1, and Q2 conduct equal collector currents. However, there is a slight problem with this assumption: The collector-to-emitter voltages of Q1 and Q2 are not equal, which introduces a current offset or a systematic error. The problem can be solved by adding a diode-connected transistor in series with the collector of Q2, as is shown for the MOS version.
Analysis to determine the output resistance of the Wilson mirror is illustrated in Fig. 44(b), from which we see that
Finally, we note that the Wilson mirror is preferred over the cascode circuit because the latter has the same dependence on β as the simple mirror. However, like the cascode mirror, the Wilson mirror requires an additional VBE drop for its operation; that is, for proper operation we must allow for 1 V or so across the Wilson-mirror output.
EXERCISE
For β= 100 and r0 ≈ 100 kW, contrast the Wilson mirror and the simple mirror by evaluating the transfer-ratio error due to finite β and the output resistance.
Ans. Transfer-ratio error: 0.02% for Wilson as opposed to 2% for the simple circuit; R0 =
5 MW for Wilson compared to 100 kW for the simple circuit.
The Wilson MOS Mirror
Figure 45(a) shows the MOS version of the Wilson mirror. Obviously there is no β error to reduce here, and the advantage of the MOS Wilson lies in its enhanced output resistance, The analysis shown in Fig. 45(b) provides
where we have neglected, for simplicity, the body effect in Q3. The output resistance is approximately the same as that achieved in the cascode circuit. Finally, to balance the two branches of the mirror and thus avoid the systematic current error
The design and advantages of the Widlar current source are illustrated below:
EXAMPLE
Figure 47 shows two circuits for generating a constant current Io = 10µA which operate from 10-V supply. Determine the values of the required resistors assuming that VBE is 0.7 V at a current of l mA and neglecting the effect of finite β.
Solution
For the basic current-source circuit in Fig. 47(a) we choose a value for R1, to result in IREF = 10µA. At this current, the voltage drop across Q1 will be
From the above example we observe that using the Widlar circuit allows the generation of a small constant current using relatively small resistors. This is an important advantage which leads to considerable savings in chip area. In fact the circuit of Fig. 47(a), requiring a 942-kW resistance, is totally impractical for implementation in IC form.
Another important characteristic of the Widlar current source is that its output resistance, is high. The increase in the output resistance, above that achieved in the basic current source, is due to the emitter degeneration resistance RE. To determine the output resistance of Q2, we assume that since the base of Q2 is connected to ground via the small resistance re of Q1, the incremental voltage at the base will be small. Thus we can use the formula derived in the CB amplifier for output resistance and adapt it for our purposes a as follows:
Thus the output resistance is increased above r0 by a factor that is very significant.
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