Digital cmos logic circuits: pass-transistor logic circuits and dynamic logic circuits.
4 PASS-TRANSISTOR LOGIC CIRCUITS
Simple approach for implementing logic functions utilizes series and parallel combinations of switches that are controlled by Input logic variables to connect the input and output nodes (see Fig. 20). Each of the switches can be implemented either by a single NMOS transistor (Fig. 21(a)) or by a pair of complementary MOS transistors connected in what is known as the CMOS transmission-gate configuration (Fig.21(b)).
This form of logic utilizes MOS transistors in the series path from input to output, to pass or block signal transmission, it is known as pass-transistor logic (PTL). As mentioned earlier, CMOS transmission gates are frequently employed to implement the switches, giving this logic-circuit form the alternative name, transmission-gate logic.
4.1 An Essential Design Requirement
An essential requirement in the design of PTL circuits is ensuring that every- circuit node has at all times a low-resistance path to VDD or ground. Consider the situation depicted in Fig. 22(a); A switch S1 (usually part of a larger PTL network, not shown) is used to form the AND function of its controlling variable B and the variable A available at the output of a CMOS inverter. The output Y of the PTL circuit is shown connected to the input of another inverter. Obviously, if B is high, S1 closes and Y = A. Node Y will then be connected either to VDD (if A is high) through Q2 or to ground (if A is low) through Q1.
But, what happens when B goes low and S1 opens? Node Y will now become a high-impedance node. If initially, vY was zero, it will remain so. However, if initially, vY was high at VDD this voltage will be maintained by the charge on the parasitic capacitance C, but for only a time: The inevitable leakage currents will slowly discharge C, and vY will diminish correspondingly. In any case, the circuit can no longer be considered a static combinational logic circuit.
The problem can be easily solved by establishing for node Y a low-resistance path that is activated when B goes low, as shown in Fig. 22(b), Here, another switch. S2 controlled by B is connected between Y and ground. When B goes low, S2 closes and establishes a low- resistance path between Y and ground,
4.2 Operation with NMOS Transistors as Switches
PTL circuit with single NMOS transistors results in a simple circuit with small area and small node capacitances. Consider the circuit shown in Fig.23, where an NMOS transistor Q is used to implement a switch connecting an input node with voltage vj and an output node. The total capacitance between the output node and ground is represented by capacitor C. The switch is shown in the closed state with the control signal applied to its gate being high at VDD. The operation of the circuit as the input voltage Vi goes high (to VDD) at time t = 0. We assume that initially the output voltage vO is zero and capacitor C is fully discharged.
The propagation delay tPLH of the PTL gate of Fig. 23 can be determined as the time for vo to reach VDD/2.
Figure 24 shows the NMOS switch circuit when vj is brought down to 0 V, assume that initially vO = VDD. Thus at t = 0+, the transistor conducts and operates in the saturation region,
Since the source is now at 0 V (note that the drain and source have interchanged roles), there will be no body effect, and Vt remains constant at Vto. As C discharges, vO decreases and the transistor enters the triode region at vO= (VDD-Vt). The capacitor discharge continues until C is fully discharged and vO= 0. Thus, the NMOS transistor provides VOL = 0, or a "good 0." Again, the propagation delay tPHL can be determined.
4.3 The Use of CMOS Transmission Gates as Switches
Great improvements in static and dynamic performance are obtained when the switches are implemented with CMOS transmission gates. The transmission gate utilizes a pair of complementary transistors connected in parallel. It acts as an excellent switch, providing bidirectional current flow, and it exhibits an on-resistance that remains almost constant for wide ranges of input voltage. These characteristics make the transmission gate not only an excellent switch in digital applications but also an excellent analog switch in such applications as data converters and switched-capacitor filters.
Figure 25(a) shows the transmission-gate switch in the "on" position with the input,Vi, rising to VDD at t = 0. Assuming, as before, that initially the output voltage is zero, we see that QN will be operating in saturation and providing a charging current of
Transistor QN will conduct a diminishing current that reduces to zero at vO=VDD- Vtn. Observe, however, that Qp operates with VSG=VDD and is initially in saturation,
where, since the body of Qp is connected to VDD-|Vtp| remains constant at the value Vto, assumed to be the same value as for the n-channel device. The total capacitor-charging current is the sum of iDN and iDp. Now, Qp will enter the triode region at vO= | Vtp |, but will continue to conduct until C is fully charged and vO=VOH =VDD , Thus, the P-channel device will provide the gate with a "good 1." The value of tPLH can be calculated using usual techniques. Note, however, that adding the PMOS transistor increases the value of C.
When vi goes low, as shown in Fig.25(b)
Figure 25 Operation of the transmission gate as a switch in PTL circuits with (a) vI high and (b) vI low.
QN and QP interchange roles. Analysis of the circuit in Fig.25(b) will indicate that QP will cease conduction when vO falls to |Vtp|, where |Vtp|is given by
Transistor QN, however, continues to conduct until C is fully discharged and vO = VOL = 0 V,a "good 0."
We conclude that transmission gates provide far superior performance, both static and dynamic, than is possible with single NMOS switches. The Disadvantage is increased circuit complexity, area, and capacitance.
4.4 Pass-Transistor Logic Circuit Examples
Figure 26 shows a PTL realization of a two-to-one multiplexer: Depending on the logic value of C, either A or B is connected to the output Y. The circuit realizes the Boolean function
Figure 26 Realization of a two-to-one multiplexer using pass-transistor logic.
Our second example is an efficient realization of the exclusive-OR (XOR) function. The circuit shown in Fig. 27, utilizes four transistors in the transmission gates and another four for the two inverters needed to generate the complements A and B, for a total of eight transistors. Note that 12 transistors are needed in the realization with complementary CMOS.
Figure 27 Realization of the XOR function using pass-transistor logic.
Our final PTL example is the circuit shown in Fig. 28. It uses NMOS switches with low or zero threshold. Observe that both the input variables and their complements are employed and that the circuit generates both the Boolean function and its complement. Thus this form of circuit is known as complementary pass-transistor logic (CPL). The circuit consists of two identical networks of pass transistors with the corresponding transistor gates controlled by the same signal (B and B). The inputs to the PTL. however, are complemented: A and B for the first network, and A and B for the second. The circuit shown realizes both the AND and NAND functions.
Figure 28 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic or CPL. Note that both the output function and its complement are generated.
5 DYNAMIC LOGIC CIRCUITS
To place dynamic-logic-circuit techniques into perspective, let's take stock of the various logic-circuit styles we have studied.
Complementary CMOS excels in nearly every performance category: It is easy to design, has the maximum possible logic swing, is robust from a noise-immunity standpoint, dissipates no static power, and can be designed to provide equal low-to-high and high-to-low propagation delays. Its main disadvantage is the requirement of two transistors for each additional gate input, which for high fan-in gates can make the chip area large and increase the total capacitance and, correspondingly, the propagation delay and the dynamic power dissipation.
Pseudo-NMOS reduces the number of required transistors at the expense of static power dissipation. Pass-transistor logic can result in simple small-area circuits but is limited to special applications and requires the use of complementary inverters to restore signal levels, especially when the switches are simple NMOS transistors.
The dynamic logic techniques is to maintain the low device count of pseudo-NMOS while reducing the static power dissipation to zero. This is achieved at the expense of more complex, and less robust, design.
5.1 Basic Principle
Figure 29(a) shows the basic dynamic-logic gate. It consists of a pull-down network (PDN) that realizes the logic function in exactly the same way as the PDN of a complementary CMOS gate or a pseudo-NMOS gate. Here, however, we have two switches in series that are periodically operated by the clock signal whose waveform is shown in Fig. 29(b). When is low, QP is turned on, and the circuit is said to be in the setup or precharge phase. When is high, QP is off and Qe turns on, and the circuit is in the evaluation phase. Finally, note that CL, denotes the total capacitance between the output node and ground.
During precharge, QP conducts and charges capacitance CL so that, at the end of the precharge interval, the voltage at Y is equal to VDD. Also during precharge, the inputs A, B, and C are allowed to change and settle to their proper values. Observe that because Qe is off, no path to ground exists.
During the evaluation phase, QP is off and Qe is turned on. Now, if the input combination is one that corresponds to a high output, the PDN does not conduct (just as in a complementary CMOS gate) and the output remains high at VDD thus VOH = VDD. Observe that no low-to-high propagation delay is required, thus tPLH= 0. On the other hand, if the combination of inputs is one that corresponds to a low output, the appropriate NMOS transistors in the PDN will conduct and establish a path between the output node and ground through the on-transistor Qe. Thus CL will be discharged through the PDN, and the voltage at the output node will reduce to VOL= 0 V. The high-to-low propagation delay tPHL can be calculated in exactly the same way as for a complementary CMOS circuit except that here we have an additional transistor, Qe, in the series path to ground.
Output Voltage Decay Due to Leakage Effects
In the absence of a path to ground through the PDN, the output voltage will ideally remain high at VDD .This, however, is based on the assumption that the charge on CL will remain intact. In practice, there will be leakage current that will cause CL to slowly discharge and vγ to decay. The principal source of leakage is the reverse current of the reverse-biased junction between the drain diffusion of transistors connected to the output node and the substrate. Such currents can be in the range of 10-12 A to 10-15 A, and they increase rapidly with temperature (approximately doubling for every 10°C rise in temperature). Thus the circuit can malfunction if the clock is operating at a very low frequency and the output node is not "refreshed" periodically.
Charge Sharing
There is another and often more serious way for CL to lose some of its charge and thus cause vγ to fall significantly below VDD. To see how this can happen, refer to Fig.30,
which shows only Q1 and Q2, the two top transistors of the PDN, together with the precharge transistor QP. Here, C1 is the capacitance between the common node of Q1 and Q2 and ground. At the beginning of the evaluation phase, after QP has turned off and with CL charged to VDD (Fig.30), we assume that C1 is initially discharged and that the inputs are such that at the gate of Q1 we have a high signal, whereas at the gate of Q2 the signal is low. We can easily see that Q1 will turn on, and its drain current,iD1 will flow as indicated.
Thus iD1 will discharge CL and charge C1. Although eventually iD1 will reduce to zero, CL will have lost some of its charge, which will have been transferred to C1. This phenomenon is known as charge sharing.
Figure 30 Charge sharing.
A serious problem arises if one attempts to cascade dynamic logic gates. Consider the situation depicted in Fig.31, where two single-input dynamic gates are connected in cascade. During the precharge phase, CL1 and CL2 will be charged through QP1 and QP2 respectively. Thus, at the end of the precharge interval, Vγ1=VDD and Vγ2=VDD. Now consider what happens in the evaluation phase for the case of high input A. Obviously, the correct result will be Y1 low (Vγ1= 0 V) and Y2 high ( Vγ2= VDD). As the evaluation phase begins, Q1 turns on and CL1 begins to discharge. However, simultaneously, Q2 turns on and CL2 also begins to discharge. Only when Vγ1 drops below Vtn will Q2 turn off. Unfortunately, however, by that time, CL2 will have lost a significant amount of its charge, and Vγ2 will be less than the expected value of VDD.( It is important to note that in dynamic logic, once charge has been lost, it cannot be recovered.)
5.3 Domino CMOS Logic
Domino CMOS logic is a form of dynamic logic that results in cascadable gates. Figure 32 shows the structure of the Domino CMOS logic gate. We observe that it is simply the basic dynamic-logic gate of Fig.29(a) with a static CMOS inverter connected to its output. Operation of the gate is straightforward. During precharge, X will be raised to VDD, and the gate output Y will be at 0V. During evaluation, depending on the combination of the input variables, either X will remain high and thus the output Y will remain low(tPHL =0) or X will be brought down to 0V and the output Y will rise to VDD (tPLH finite). Thus, during evaluation, the output either remains low or makes only one low-to-high transition.
Consider the situation in Fig.33(a), where we show two Domino gates connected in cascade. For simplicity, we show single input gates. At the end of prechage, X1 will be at VDD, Y1 will be at 0V, X2 will be at VDD, and Y2 will be at 0V.As the preceding case, assume A is high at the beginning of evaluation. Thus, as goes up, capacitor CL1 will begin discharging, pulling X1down. Meanwhile, the low input at the gate of Q2 keeps Q2 off, and CL2 remains fully charged. When vX1 falls below the threshold voltage of inverter I1, Y1 will go up turning Q2 on, which in turn begins to discharge CL2 and pulls X2 low. Eventually, Y2 rises to VDD.
From this description, we see that because the output of the Domino gate is low at the beginning of evaluation, no premature capacitor discharge will occur in the subsequent gate in the cascade. As indicated in Fig.33(b), output Y1 will make a 0-to-1 transition tPLH seconds after the rising edge of the clock. Subsequently, output Y2 makes a 0-to-1 transition after another tPLH interval.
Figure 10.33(a) Two single-input domino CMOS logic gates connected in cascade. (b) Waveforms during the evaluation phase.
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